參數(shù)資料
型號： MSC7119VM1200
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 0-BIT, 300 MHz, OTHER DSP, PBGA400
封裝： LEAD FREE, MAPBGA-400
文件頁數(shù)： 38/60頁
文件大?。?/td> 1138K
代理商： MSC7119VM1200
Hardware Design Considerations
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
43
3.2.2.1
Case 1
The power-up sequence is as follows:
1.
Turn on the VDDIO (3.3 V) supply first.
2.
Turn on the VDDC (1.2 V) supply second.
3.
Turn on the VDDM (2.5 V) supply third.
4.
Turn on the VREF (1.25 V) supply fourth (last).
The power-down sequence is as follows:
1.
Turn off the VREF (1.25 V) supply first.
2.
Turn off the VDDM (2.5 V) supply second.
3.
Turn off the VDDC (1.2 V) supply third.
4.
Turn of the VDDIO (3.3 V) supply fourth (last).
Use the following guidelines:
Make sure that the time interval between the ramp-down of VDDIO and VDDC is less than 10 ms.
Make sure that the time interval between the ramp-up or ramp-down for VDDC and VDDM is less than 10 ms for
power-up and power-down.
Refer to Figure 30 for relative timing for power sequencing case 1.
Figure 30. Voltage Sequencing Case 1
Time
Vo
lt
a
g
e
Ramp-down
Ramp-up
VDDIO = 3.3 V
VDDM = 2.5 V
VDDC = 1.2 V
VREF = 1.25 V
<10 ms
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