參數(shù)資料
型號(hào): MSC7119VM1200
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 0-BIT, 300 MHz, OTHER DSP, PBGA400
封裝: LEAD FREE, MAPBGA-400
文件頁(yè)數(shù): 50/60頁(yè)
文件大小: 1138K
代理商: MSC7119VM1200
MSC7119 Data Sheet, Rev. 8
Hardware Design Considerations
Freescale Semiconductor
54
3.5
DDR Memory System Guidelines
MSC7119 devices contain a memory controller that provides a glueless interface to external double data rate (DDR) SDRAM
memory modules with Class 2 Series Stub Termination Logic 2.5 V (SSTL_2). There are two termination techniques, as shown
in Figure 36. Technique B is the most popular termination technique.
Figure 37 illustrates the power wattage for the resistors. Typical values for the resistors are as follows:
RS = 22
Ω
RT = 24
Ω
Figure 36. SSTL Termination Techniques
Controller
Address
Command
Chip Selects
Data
Strobes
Mask
VREF
VT
T
e
rm
ina
tor
VTT
Generator
DDR
Bank
DDR
Bank
VTT
SSTL_2
RS
RT
RS
Controller
Address
Command
Chip Selects
Data
Strobes
Mask
VTT
T
e
rmi
nat
or
Is
la
nd
VTT
Generator
DDR
Bank
DDR
Bank
SSTL_2
RS
RT
RS
Technique A
Technique B
相關(guān)PDF資料
PDF描述
MSC8102M4000 32-BIT, 75 MHz, OTHER DSP, CBGA431
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MSC8122MP8000 32-BIT, 500 MHz, OTHER DSP, PBGA431
MSC8144ETVT800B 133 MHz, OTHER DSP, PBGA783
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