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參數資料
| 型號： | MSC7119VM1200 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | 0-BIT, 300 MHz, OTHER DSP, PBGA400 |
| 封裝： | LEAD FREE, MAPBGA-400 |
| 文件頁數： | 32/60頁 |
| 文件大小： | 1138K |
| 代理商： | MSC7119VM1200 |
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MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
38
2.5.11
Event Timing
Figure 24 shows the signal behavior of the EVNT pins.
2.5.12
GPIO Timing
Table 29. EVNT Signal Timing
Number
Characteristics
Type
Min
67
EVNT as input
Asynchronous
1.5
× APBCLK periods
68
EVNT as output
Synchronous to core clock
1 APBCLK period
Notes:
1.
Refer to Table 27 for a definition of the APBCLK period.
2.
Direction of the EVNT signal is configured through the GPIO and Event port registers.
3.
Refer to the signal chapter in the MSC711x Reference Manual for details on EVNT pin functionality.
Figure 24. EVNT Pin Timing
Table 30. GPIO Signal Timing1,2,3
Number
Characteristics
Type
Min
601
GPI4.5
Asynchronous
1.5
× APBCLK periods
602
GPO5
Synchronous to core clock
1 APBCLK period
603
Port A edge-sensitive interrupt
Asynchronous
1.5
× APBCLK periods
604
Port A level-sensitive interrupt
Asynchronous
3
× APBCLK periods6
Notes:
1.
Refer to Table 27 for a definition of the APBCLK period.
2.
Direction of the GPIO signal is configured through the GPIO port registers.
3.
Refer to Section 1.5 for details on GPIO pin functionality.
4.
GPI data is synchronized to the APBCLK internally and the minimum listed is the capability of the hardware to capture data
into a register when the GPADR is read. The specification is not tested due to the asynchronous nature of the input and
dependence on the state of the DSP core. It is guaranteed by design.
5.
The output signals cannot toggle faster than 75 MHz.
6.
Level-sensitive interrupts should be held low until the system determines (via the service routine) that the interrupt is
acknowledged.
Figure 25. GPI/GPO Pin Timing
EVNT in
67
EVNT out
68
GPI
601
GPO
602
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