參數資料
型號: MSC7119VM1200
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數字信號處理
英文描述: 0-BIT, 300 MHz, OTHER DSP, PBGA400
封裝: LEAD FREE, MAPBGA-400
文件頁數: 18/60頁
文件大?。?/td> 1138K
代理商: MSC7119VM1200
Electrical Characteristics
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
25
2.5.3.2
Reset Configuration
The MSC7119 has two mechanisms for writing the reset configuration:
From a host through the host interface (HDI16)
From memory through the I2C interface
Five signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the boot and
operating conditions:
BM[0–1]
SWTE
H8BIT
HDSP
2.5.3.3
Reset Timing Tables
Table 16 and Figure 4 describe the reset timing for a reset configuration write.
Table 16. Timing for a Reset Configuration Write
No.
Characteristics
Expression
Unit
1
Required external PORESET duration minimum
16/FCLKIN
clocks
2
Delay from PORESET deassertion to HRESET deassertion
521/FCLKIN
clocks
Note:
Timings are not tested, but are guaranteed by design.
Figure 4. Timing Diagram for a Reset Configuration Write
PORESET
Internal
HRESET
Input
Output(I/O)
Configuration Pins
are sampled
2
1
相關PDF資料
PDF描述
MSC8102M4000 32-BIT, 75 MHz, OTHER DSP, CBGA431
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MSC8122TVT4800V 32-BIT, 300 MHz, OTHER DSP, PBGA431
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