參數(shù)資料
型號(hào)： MSC8101VT1375F
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 31/104頁(yè)
文件大?。?/td> 0K
描述： IC DSP 16BIT 250MHZ 332-FCPBGA
標(biāo)準(zhǔn)包裝： 90
系列： StarCore
類(lèi)型： SC140 內(nèi)核
接口： 通信處理器模塊（CPM）
時(shí)鐘速率： 275MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.60V
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 332-BFBGA，F(xiàn)CPBGA
供應(yīng)商設(shè)備封裝： 332-FCBGA（17x17）
包裝： 托盤(pán)
MSC8101 Technical Data, Rev. 19
1-28
Freescale Semiconductor
Signals/Connections
PC24
BRG8O
CLK8
TIN3
Timer4: TOUT4
DMA: DREQ2
Output
Input
Output
Input
Baud-Rate Generator 8 Output
The CPM supports up to 8 BRGs used internally by the bank-of-clocks
selection logic and/or to provide an output to one of the 8 BRG pins.
Clock 8
The CPM supports up to 10 clock input pins. The clocks are sent to the
bank-of-clocks selection logic, where they can be routed to the controllers.
Timer Input 3
A timer can have one of the following sources: another timer, system
clock, system clock divided by 16, or a timer input. The CPM supports up
to four timer inputs. The timer inputs can be captured on the rising, falling,
or both edges.
Timer 4: Timer Out 4
The timers (Timer1–4]) can output a signal on a timer output (TOUT[1–4])
when the reference value is reached. This signal can be an active-low
pulse or a toggle of the current output. The output can also be connected
internally to the input of another timer, resulting in a 32-bit timer.
DMA: Data Request 2
DACK2, DREQ2, DRACK2, and DONE2 belong to the SIU DMA controller.
DONE2 and DRACK2 are signals on the same pin and therefore cannot be
used simultaneously. There are two sets of DMA pins associated with the
PIO ports.
PC23
CLK9
DMA: DACK1
EXT2
Input
Output
Input
Clock 9
The CPM supports up to 10 clock input pins sent to the bank-of-clocks
selection logic, where they can be routed to the controllers.
DMA: Data Acknowledge 1
DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA controller.
DONE1 and DRACK1 are signals on the same pin and therefore cannot be
used simultaneously. There are two sets of DMA pins associated with the
PIO ports.
External Request 2
External request input line 2 asserts an internal request to the CPM
processor. The signal can be programmed as level- or edge-sensitive, and
also has programmable priority. Refer to the risc controller configuration
register (RCCR) description in the Chapter 17 of the MSC8101 Reference
Manual for programming information. There are no current microcode
applications for this request line. It is reserved for future development.
Table 1-9.
Port C Signals (Continued)
Name
Dedicated
I/O Data
Direction
Description
General-
Purpose I/O
Peripheral Controller:
Dedicated I/O
Protocol
相關(guān)PDF資料
PDF描述
EBC10DRXS CONN EDGECARD 20POS DIP .100 SLD
TACA107M004RTA CAP TANT 100UF 4V 20% 1206
HCC07DRXI CONN EDGECARD 14POS DIP .100 SLD
FMC13DRAH CONN EDGECARD 26POS R/A .100 SLD
EMM44DRXS CONN EDGECARD 88POS DIP .156 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MSC8101VT1500F 功能描述:IC DSP 16BIT 250MHZ 332-FCPBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類(lèi)型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類(lèi)型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤(pán)
MSC8102 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor
MSC81020 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:RF & MICROWAVE TRANSISTORS GENERAL PURPOSE AMPLIFIER APPLICATIONS
MSC8102M4000 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor
MSC8102M4400 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*