參數(shù)資料
型號(hào)： MSC8101VT1375F
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 44/104頁(yè)
文件大?。?/td> 0K
描述： IC DSP 16BIT 250MHZ 332-FCPBGA
標(biāo)準(zhǔn)包裝： 90
系列： StarCore
類(lèi)型： SC140 內(nèi)核
接口： 通信處理器模塊（CPM）
時(shí)鐘速率： 275MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.60V
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 332-BFBGA，F(xiàn)CPBGA
供應(yīng)商設(shè)備封裝： 332-FCBGA（17x17）
包裝： 托盤(pán)
MSC8101 Technical Data, Rev. 19
2-4
Freescale Semiconductor
Physical and Electrical Specifications
2.5 Clock Configuration
The following sections provide a general description of clock configuration.
2.5.1
Valid Clock Modes
Table 2-6 shows the maximum frequency values for each rated core frequency (250, 275, or 300 MHz). The user
must ensure that maximum frequency values are not exceeded.
Six bit values map the MSC8101 clocks to one of the valid configuration mode options. Each option determines the
CLKIN
, SC140, system bus, SCC clock, CPM, and CLKOUT frequencies. The six bit values are derived from three
dedicated input pins (MODCK[1–3]) and three bits from the hard reset configuration word (MODCK_H). To
configure the SPLL pre-division factor, SPLL multiplication factor, and the frequencies for the SC140, SCC
clocks, CPM parallel I/O ports, and system buses, the MODCK[1–3] pins are sampled and combined with the
MODCK_H values when the internal power-on reset (internal PORESET) is deasserted. Clock configuration
changes only when the internal PORESET signal is deasserted. The following factors are configured:
SPLL pre-division factor (SPLL PDF)
SPLL multiplication factor (SPLL MF)
Bus post-division factor (Bus DF)
CPM division factor (CPM DF)
Core division factor (Core DF)
CPLL pre-division factor (CPLL PDF)
CPLL multiplication factor (CPLL MF)
The SCC division factor (SCC DF) is fixed at 4. The BRG division factor (BRG DF) is configured through the
System Clock Control Register (SCCR) and can be 4, 16 (default after reset), 64, or 256.
Note:
Refer to Clock Mode Selection for MSC8101 and MSC8103 Mask Set 2K87M (AN2306) for details on
clock configuration.
2.5.2
Clocks Programming Model
This section describes the clock registers in detail. The registers discussed are as follows:
System Clock Control Register (SCCR)
System Clock Mode Register (SCMR)
Table 2-6.
Maximum Frequencies
Characteristic
Maximum Frequency in MHz
Core Frequency
250
275
300
CPM Frequency (CPMCLK)
166.67
183.33
200
Bus Frequency (BCLK)
83.33
91.67
100
Serial Communication Controller Clock Frequency (SCLK)
83.33
91.67
100
Baud Rate Generator Clock Frequency (BRGCLK)
83.33
91.67
100
External Clock Output Frequency (CLKOUT)
83.33
91.67
100
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