Host reset configuration all" />
參數(shù)資料
型號(hào)： MSC8101VT1375F
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 52/104頁(yè)
文件大?。?/td> 0K
描述： IC DSP 16BIT 250MHZ 332-FCPBGA
標(biāo)準(zhǔn)包裝： 90
系列： StarCore
類型： SC140 內(nèi)核
接口： 通信處理器模塊（CPM）
時(shí)鐘速率： 275MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.60V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 332-BFBGA，F(xiàn)CPBGA
供應(yīng)商設(shè)備封裝： 332-FCBGA（17x17）
包裝： 托盤
AC Timings
MSC8101 Technical Data, Rev. 19
Freescale Semiconductor
2-11
2.6.4.3 Host Reset Configuration
Host reset configuration allows the host to program the reset configuration word via the Host port after PORESET is
deasserted, as described in the MSC8101 Reference Manual. The MSC8101 samples the signals described in Table
2-13 one the rising edge of PORESET when the signal is deasserted.
If HPE is sampled high, the host port is enabled. In this mode the RSTCONF pin must be pulled up. The device
extends the internal PORESET until the host programs the reset configuration word register. The host must write
four 8-bit half-words to the Host Reset Configuration Register address to program the reset configuration word,
which is 32 bits wide. For more information, see the MSC8101 Reference Manual. The reset configuration word is
programmed before the internal PLL and DLL in the MSC8101 are locked. The host must program it after the
rising edge of the PORESET input. In this mode, the host must have its own clock that does not depend on the
MSC8101 clock. After the PLL and DLL are locked, HRESET remains asserted for another 512 bus clocks and is
then released. The SRESET is released three bus clocks later (see Figure 2-7).
2.6.4.4 Hardware Reset Configuration
Hardware reset configuration is enabled if HPE is sampled low at the rising edge of PORESET. The value driven on
RSTCONF
while PORESET changes from assertion to deassertion determines the MSC8101 configuration. If
RSTCONF
is deasserted (driven high) while PORESET changes, the MSC8101 acts as a configuration slave. If
6
Delay from SPLL lock to SRESET deassertion
DLL enabled
— BCLK = 18 MHz
— BCLK = 75 MHz
DLL disabled
— BCLK = 18 MHz
— BCLK = 75 MHz
3588
/ BLCK
515
/ BLCK
199.33
47.84
28.61
6.87
μs
Note:
Value given for lowest possible CLKIN frequency 18 MHz to ensure proper initialization of reset sequence.
Figure 2-7.
Host Reset Configuration Timing
Table 2-14.
Reset Timing (Continued)
No.
Characteristics
Expression
Min
Max
Unit
PORESET
Internal
HRESET
Input
Output (I/O)
SRESET
Output (I/O)
HRESET/SRESET are
extended for 512/515 BUS
clocks, respectively, from PLL
and DLL lock
PLL locks after
800 SPLLMFCLKs and
DLL locks 3073 BUS clocks
after PLL is locked.
When DLL is disabled,
reset period is shortened by
DLL lock time.
RSTCONF, HPE
pins are sampled
HRM, BTM
Any time
Host programs
Word
MODCK_H bits
are ready for PLL.
MODCK[1–3] pins
are sampled.
PORESET
Reset Configuration
1
2
3
5
4
6
asserted for
min 16
CLKIN.
PLL locked
DLL locked
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