參數(shù)資料
型號： MSC8101VT1375F
廠商： Freescale Semiconductor
文件頁數(shù)： 38/104頁
文件大?。?/td> 0K
描述： IC DSP 16BIT 250MHZ 332-FCPBGA
標(biāo)準(zhǔn)包裝： 90
系列： StarCore
類型： SC140 內(nèi)核
接口： 通信處理器模塊（CPM）
時鐘速率： 275MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.60V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 332-BFBGA，F(xiàn)CPBGA
供應(yīng)商設(shè)備封裝： 332-FCBGA（17x17）
包裝： 托盤
CPM Ports
MSC8101 Technical Data, Rev. 19
Freescale Semiconductor
1-35
PD17
BRG2O
FCC1: RXPRTY
UTOPIA
SPI: SPIMOSI
Output
Input
Input/ Output
Baud Rate Generator 2 Output
The CPM supports up to 8 BRGs for use internally to the MSC8101
and/or to provide an output to one of the 8 BRG pins.
FCC1: UTOPIA Receive Parity
This is the odd parity bit for RXD[0–7].
SPI: Master Output Slave Input
The SPI interface comprises our signals: master out slave in (SPIMOSI),
master in slave out (SPIMISO), clock (SPICLK) and select (SPISEL).
The SPI can be configured as a slave or master in single- or multiple-
master environments. When the SPI is a slave, SPICLK is the clock
input that shifts received data in from SPIMOSI and transmitted data out
through SPIMISO.
PD16
FCC1: TXPRTY
UTOPIA
SPI: SPIMISO
Output
Input/ Output
FCC1: UTOPIA Transmit Parity
This is the odd parity bit for TXD[0–7].
SPI: Master Input Slave Output
The SPI interface comprises four signals: master out slave in
(SPIMOSI), master in slave out (SPIMISO), clock (SPICLK), and select
(SPISEL). The SPI can be configured as a slave or master in single- or
multiple-master environments. When the SPI is a slave, SPICLK is the
clock input that shifts received data in from SPIMOSI and transmitted
data out through SPIMISO.
PD7
SMC1: SMSYN
FCC1: TXADDR3
UTOPIA master
FCC1: TXADDR3
UTOPIA slave
FCC1: TXCLAV2
UTOPIA multi-PHY master, direct
polling
Input
Output
Input
SMC1: Serial Management Synchronization
The SMC interface consists of SMTXD, SMRXD, SMSYN and a clock.
Not all signals are used for all applications. SMCs are full-duplex ports
that support three protocols or modes: UART, transparent or general-
circuit interface (GCI).
FCC1: UTOPIA Master Transmit Address Bit 3
This is master transmit address bit 3.
FCC1: UTOPIA Slave Transmit Address Bit 3
This is slave transmit address bit 3.
FCC1: UTOPIA Multi-PHY Master Transmit Cell Available 2 Direct
Polling
Asserted by an external UTOPIA slave PHY to indicate that it can accept
one complete ATM cell.
Table 1-10.
Port D Signals (Continued)
Name
Dedicated
I/O Data
Direction
Description
General-
Purpose I/O
Peripheral Controller:
Dedicated I/O
Protocol
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