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參數(shù)資料
| 型號： | MSC8101VT1375F |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 34/104頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 16BIT 250MHZ 332-FCPBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | StarCore |
| 類型： | SC140 內(nèi)核 |
| 接口： | 通信處理器模塊（CPM） |
| 時鐘速率： | 275MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 512kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.60V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 332-BFBGA，F(xiàn)CPBGA |
| 供應(yīng)商設(shè)備封裝： | 332-FCBGA（17x17） |
| 包裝： | 托盤 |
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CPM Ports
MSC8101 Technical Data, Rev. 19
Freescale Semiconductor
1-31
PC7
SI2: L1ST1
FCC1: CTS
HDLC serial, HDLC nibble,
and transparent
FCC1: TXADDR2
UTOPIA master
FCC1: TXADDR2
UTOPIA slave
FCC1: TXCLAV1
UTOPIA multi-PHY master, direct
polling
Output
Input
Output
Input
Serial Interface 2: Strobe 1
The MSC8101 time-slot assigner supports up to four strobe outputs that
can be asserted on a bit or byte basis. The strobe outputs are useful for
interfacing to other devices that do not support the multiplexed interface or
for enabling/disabling three-state I/O buffers in a multiple-transmitter
architecture. These strobes can also generate output wave forms for such
applications as stepper-motor control.
FCC1: Clear To Send
In the standard modem interface signals supported by FCC1 (RTS, CTS,
and CD). CTS is asynchronous with the data.
FCC1: UTOPIA Multi-PHY Master Transmit Address Bit 2
This is master transmit address bit 2.
FCC1: UTOPIA Multi-PHY Slave Transmit Address Bit 2
This is slave transmit address bit 2.
FCC1: UTOPIA Multi-PHY Master Transmit Cell Available 1 Direct
Polling
Asserted by an external UTOPIA slave PHY to indicate that it can accept
one complete ATM cell.
PC6
SI2: L1ST2
FCC1: CD
HDLC serial, HDLC nibble,
and transparent
FCC1: RXADDR2
UTOPIA master
FCC1: RXADDR2
UTOPIA slave
FCC1: RXCLAV1
UTOPIA multi-PHY master, direct
polling
Output
Input
Output
Input
Serial Interface 2: Layer 1 Strobe 2
The MSC8101 time-slot assigner supports up to four strobe outputs that
can be asserted on a bit or byte basis. The strobe outputs are useful for
interfacing to other devices that do not support the multiplexed interface or
for enabling/disabling three-state I/O buffers in a multiple-transmitter
architecture. These strobes can also generate output wave forms for such
applications as stepper-motor control.
FCC1: Carrier Detect
In the standard modem interface signals supported by FCC1 (RTS, CTS,
and CD). CD is an input asynchronous with the data.
FCC1: UTOPIA Multi-PHY Master Receive Address Bit 2
This is master receive address bit 2.
FCC1: UTOPIA Slave Receive Address Bit 2
This is slave receive address bit 2.
FCC1: UTOPIA Multi-PHY Master Receive Cell Available 1 Direct
Polling
Asserted by an external PHY when one complete ATM cell is available for
transfer.
Table 1-9.
Port C Signals (Continued)
Name
Dedicated
I/O Data
Direction
Description
General-
Purpose I/O
Peripheral Controller:
Dedicated I/O
Protocol
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| MSC8101VT1500F | 功能描述:IC DSP 16BIT 250MHZ 332-FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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