參數(shù)資料
型號: MT18VDDT12872PHIG-265XX
元件分類: DRAM
英文描述: 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA200
封裝: SODIMM-200
文件頁數(shù): 29/39頁
文件大?。?/td> 816K
代理商: MT18VDDT12872PHIG-265XX
128MB, 256MB, 512MB, 1GB (x72, ECC, PLL)
200-PIN DDR SDRAM SODIMM
09005aef808ffdc7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD9_18C16_32_64_128X72PHG_E.fm - Rev. E 7/03 EN
35
2003 Micron Technology, Inc. All rights reserved.
Table 28:
Serial Presence- Detect Matrix (MT18VDDT6472PH and
MT18VDDT12872PH)
“1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW”
BYTE
DESCRIPTION
ENTRY(VERSION)
MT18VDDT6472PH MT18VDDT12872PH
0
Number of SPD Bytes Used by Micron
128
80
1
Total Number of Bytes in SPD Device
256
08
2
Fundamental Memory Type
SDRAM DDR
07
3
Number of Row Addresses on Assembly
13
0D
4
Number of Column Addresses on Assembly
11
0A
0B
5
Number of Physical Ranks on DIMM
202
02
6
Module Data Width
72
48
7
Module Data Width (Continued)
000
00
8
Module Voltage Interface Levels
SSTL 2.5V
04
9
SDRAM Cycle Time, tCK (CAS Latency = 2.5)
(See note 1)
6ns (-335)
7ns (-262/-26A)
7.5ns (-265)
8ns (-202)
60
70
75
80
60
70
75
80
10
SDRAM Access from Clock, tAC (CAS Latency =
2.5)
(See note 1)
0.7ns (-335)
0.75ns (-262/-26A/-265)
0.8ns (-202)
70
75
80
70
75
80
11
Module Configuration Type
ECC
02
12
Refresh Rate/ Type
7.8s/SELF
82
13
SDRAM Device Width (Primary DDR SDRAM)
x8
08
14
Error-checking DDR SDRAM Data Width
x8
08
15
Minimum Clock Delay, Back-to-Back Random
Column Access
1 clock
01
16
Burst Lengths Supported
2, 4, 8
0E
17
Number of Banks on DDR SDRAM Device
404
04
18
CAS Latencies Supported
2.5
0C
19
CS Latency
001
01
20
WE Latency
102
02
21
SDRAM Module Attributes
Unbuffered, Diff CLK,
PLL
24
22
SDRAM Device Attributes: General
Fast/concurrent auto
precharge
C0
23
SDRAM Cycle Time, tCK (CAS Latency = 2)
(See note 2)
7.5ns (-335/-26A/-262)
10ns (-265/-202)
75
A0
75
A0
24
SDRAM Access from CK, tAC (CAS Latency = 2)
(See note 2)
0.7ns (-335)
0.75ns (-262/-26A/-265)
0.8ns (-202)
70
75
80
70
75
80
25
SDRAM Cycle Time, tCK (CAS Latency = 1.5)
N/A
00
26
SDRAM Access from CK, tAC (CAS Latency = 1.5)
N/A
00
27
Minimum Row Precharge Time, tRP
18ns (-335)
15ns (-262)
20ns (-202/-265/-26A)
48
3C
50
48
3C
50
28
Minimum Row Active to Row Active, tRRD
12ns (-335)
15ns (-262/-26A/-265/-202)
30
3C
30
3C
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