參數(shù)資料
型號(hào): MT18VDDT12872PHIG-265XX
元件分類: DRAM
英文描述: 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA200
封裝: SODIMM-200
文件頁(yè)數(shù): 8/39頁(yè)
文件大?。?/td> 816K
代理商: MT18VDDT12872PHIG-265XX
128MB, 256MB, 512MB, 1GB (x72, ECC, PLL)
200-PIN DDR SDRAM SODIMM
09005aef808ffdc7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD9_18C16_32_64_128X72PHG_E.fm - Rev. E 7/03 EN
16
2003 Micron Technology, Inc. All rights reserved.
Table 14:
IDD Specifications and Conditions (MT9VDDT3272PH)
DDR SDRAM components only;
Notes: 1–5, 8, 10, 12, 48; notes appear on pages 24–27 ; 0
°C TA +70°C; VDD = VDDQ = +2.5V ±0.2V
MAX
PARAMETER/CONDITION
SYMBOL
-335
-26A/-265
-202
UNITS
NOTES
OPERATING CURRENT: One device bank; Active-Precharge;
tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs
changing once per clock cyle; Address and control inputs
changing once every two clock cycles
IDD0
1,125
945
1,080
mA
OPERATING CURRENT: One device bank; Active-Read-
Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN);
IOUT = 0mA; Address and control inputs changing once per
clock cycle
IDD1
1,530
1,305
1,395
mA
PRECHARGE POWER-DOWN STANDBY CURRENT: All device
banks idle; Power-down mode; tCK = tCK (MIN);
CKE = (LOW)
IDD2P
35
36
mA
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
tCK = tCK MIN; CKE = HIGH; Address and other control inputs
changing once per clock cycle. VIN = VREF for DQ, DQS, and
DM
IDD2F
450
405
mA
ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode; tCK = tCK (MIN);
CKE = LOW
IDD3P
270
225
270
mA
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One
device bank; Active-Precharge; tRC = RAS (MAX); tCK = tCK
(MIN); DQ, DM and DQS inputs changing twice per clock
cycle; Address and other control inputs changing once per
clock cycle
IDD3N
540
450
mA
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One device bank active; Address and control inputs
changing once per clock cycle; CK = tCK (MIN); IOUT = 0mA
IDD4R
1,575
1,350
1,575
mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One device bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and
DQS inputs changing twice per clock cycle
IDD4W
1,395
1,215
1,710
mA
AUTO REFRESH CURRENT
tRC = tRFC (MIN)
IDD5
2,295
2,115
2,205
mA
tRFC = 7.8125s
IDD5A
54
mA
SELF REFRESH CURRENT: CKE
0.2V
IDD6
36
mA
OPERATING CURRENT: Four bank interleaving READs (BL=4)
with auto precharge with, tRC = tRC (MIN); tCK = tCK (MIN);
Address and control inputs change only during Active READ,
or WRITE commands
IDD7
3,645
3,150
3,285
mA
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