參數(shù)資料
型號(hào)： MT18VDDT12872PHIG-265XX
元件分類(lèi)： DRAM
英文描述： 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA200
封裝： SODIMM-200
文件頁(yè)數(shù)： 14/39頁(yè)
文件大小： 816K
代理商： MT18VDDT12872PHIG-265XX
128MB, 256MB, 512MB, 1GB (x72, ECC, PLL)
200-PIN DDR SDRAM SODIMM
09005aef808ffdc7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD9_18C16_32_64_128X72PHG_E.fm - Rev. E 7/03 EN
21
2003 Micron Technology, Inc. All rights reserved.
Table 20:
Electrical Characteristics and Recommended AC Operating Conditions
(-335 and -262)
DDR SDRAM components only; notes appear on pages 24–27
°C TA +70°C; VDD = VDDQ = +2.5V ±0.2V
AC CHARACTERISTICS
-335
-262
UNITS
NOTES
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
Access window of DQs from CK/CK#
tAC
-0.7
+0.7
-0.75
+0.75
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
Clock cycle time
CL = 2.5
tCK (2.5)
6
13
7.5
13
ns
CL = 2
tCK (2)
7.5
13
7.5
13
ns
DQ and DM input hold time relative to DQS
tDH
0.45
0.5
ns
DQ and DM input setup time relative to DQS
tDS
0.45
0.5
ns
DQ and DM input pulse width (for each input)
tDIPW
1.75
ns
Access window of DQS from CK/CK#
tDQSCK
-0.60
+0.60
-0.75
+0.75
ns
DQS input high pulse width
tDQSH
0.35
tCK
DQS input low pulse width
tDQSL
0.35
tCK
DQS-DQ skew, DQS to last DQ valid, per group,
per access
tDQSQ
0.45
0.5
ns
Write command to first DQS latching transition
tDQSS
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK rising - setup time
tDSS
0.2
tCK
DQS falling edge from CK rising - hold time
tDSH
0.2
tCK
Half clock period
tHP
tCH, tCL
ns
Data-out high-impedance window from CK/CK#
tHZ
+0.70
+0.75
ns
Data-out low-impedance window from CK/CK#
tLZ
-0.70
-0.75
ns
Address and control input hold time (slow slew
rate)
tIH
S
0.75
0.90
ns
Address and control input setup time (slow slew
rate)
tIS
S
0.75
0.90
ns
Address and Control input pulse width (for each
input)
tIPW
2.2
ns
LOAD MODE REGISTER command cycle time
tMRD
0.80
15
ns
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
tQH
tHP -
tQHS
tHP -
tQHS
ns
Data Hold Skew Factor
tQHS
0.50
0.75
ns
ACTIVE to PRECHARGE command
tRAS
42
70,000
40
120,000
ns
ACTIVE to READ with Auto precharge command
tRAP
18
15
ns
ACTIVE to ACTIVE/AUTO REFRESH command
period
tRC
60
ns
AUTO REFRESH command period
tRFC
72
75
ns
ACTIVE to READ or WRITE delay
tRCD
18
15
ns
PRECHARGE command period
tRP
18
15
ns
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
ACTIVE bank a to ACTIVE bank b command
tRRD
12
15
ns
DQS write preamble
tWPRE
0.25
tCK
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