參數(shù)資料
型號: MT46V32M16TG-75ELIT
元件分類: DRAM
英文描述: 32M X 16 DDR DRAM, 0.75 ns, PDSO66
封裝: 0.400 INCH, PLASTIC, TSOP-66
文件頁數(shù): 20/82頁
文件大?。?/td> 2855K
代理商: MT46V32M16TG-75ELIT
512Mb: x4, x8, x16
DDR SDRAM
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN
27
2000 Micron Technology, Inc. All rights reserved.
Figure 18: READ to WRITE
NOTE:
1. DO n = data-out from column n.
2. DI b = data-in from column b.
3. Burst length = 4 in the cases shown (applies for bursts of 8 as well; if the burst length is 2, the BST command shown can
be NOP).
4. One subsequent element of data-out appears in the programmed order following DO n.
5. Data-in elements are applied following DI b in the programmed order.
6. Shown with nominal tAC, tDQSCK, and tDQSQ.
7. BST = BURST TERMINATE command, page remains open.
CK
CK#
COMMAND
READ
BST7
NOP
ADDRESS
Bank,
Col n
WRITE
Bank,
Col b
T0
T1
T2
T3
T2n
T4
T5
T4n
T5n
DQ
DQS
DM
t
(NOM)
DQSS
DI
b
CK
CK#
COMMAND
READ
BST7
NOP
WRITE
NOP
ADDRESS
Bank a,
Col n
NOP
T0
T1
T2
T3
T3n
T4
T5
T5n
DQ
DQS
DO
n
DM
DON’T CARE
TRANSITIONING DATA
DO
n
t
(NOM)
DQSS
CK
CK#
COMMAND
READ
BST7
NOP
ADDRESS
Bank,
Col n
WRITE
Bank,
Col b
T0
T1
T2
T3
T2n
T4
T5
T5n
DQ
DQS
DM
t
(NOM)
DQSS
DI
b
DO
n
NOP
CL = 2.5
CL = 2
T3n
CL = 3
DI
b
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