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參數(shù)資料
| 型號： | MT46V32M16TG-75ELIT |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP-66 |
| 文件頁數(shù)： | 40/82頁 |
| 文件大?。?/td> | 2855K |
| 代理商： | MT46V32M16TG-75ELIT |
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512Mb: x4, x8, x16
DDR SDRAM
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN
45
2000 Micron Technology, Inc. All rights reserved.
still accesses all of the data in the burst. For write with auto precharge, the precharge period
begins when tWR ends, with tWR measured as if auto precharge was disabled. The access
period starts with registration of the command and ends where the precharge period (or
tRP) begins.
3b.
This device supports concurrent auto precharge such that when a read with auto precharge
is enabled or a write with auto precharge is enabled any command to other banks is
allowed, as long as that command does not interrupt the read or write data transfer already
in process. In either case, all other related limitations apply (e.g., contention between read
data and write data must be avoided).
3c.
The minimum delay from a read or write command with auto precharge enabled, to a com-
mand to a different bank is summarized below.
NOTE:
CLRU = CAS Latency (CL) rounded up to the next integer
BL = Bust Length
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current
state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and
READs or WRITEs with auto precharge disabled.
8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be
used to end the READ burst prior to asserting a WRITE command.
FROM COMMAND
TO COMMAND
MINIMUM DELAY
(WITH CONCURRENT AUTO PRECHARGE)
WRITE w/AP
READ or READ w/AP
[1 + (BL/2)] * tCK + tWTR
WRITE or WRITE w/AP
(BL/2) * tCK
PRECHARGE
1 tCK
ACTIVE
1 tCK
READ w/AP
READ or READ w/AP
(BL/2) * tCK
WRITE or WRITE w/AP
[CLRU
+ (BL/2)] *tCK
PRECHARGE
1 tCK
ACTIVE
1 tCK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT46V32M16BN-5BLIT | 32M X 16 DDR DRAM, 0.7 ns, PBGA60 |
| MT46V32M81AZ4-6T:G | 32M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| MT47H128M8HV-187ELIT:E | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| MT47H128M8HQ-187ELAT:E | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| MT48LC2M32B1TG-7 | 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V32M16TG-75L | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M16TG-75Z | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M16TG-75ZL | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
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