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參數(shù)資料
| 型號： | MT46V32M16TG-75ELIT |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP-66 |
| 文件頁數(shù)： | 35/82頁 |
| 文件大?。?/td> | 2855K |
| 代理商： | MT46V32M16TG-75ELIT |
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512Mb: x4, x8, x16
DDR SDRAM
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN
40
2000 Micron Technology, Inc. All rights reserved.
PRECHARGE
The PRECHARGE command (Figure 31) is used to
deactivate the open row in a particular bank or the
open row in all banks. The bank(s) will be available for
a subsequent row access some specified time (tRP)
after the PRECHARGE command is issued. Input A10
determines whether one or all banks are to be pre-
charged, and in the case where only one bank is to be
precharged, inputs BA0, BA1 select the bank. When all
banks are to be precharged, inputs BA0, BA1 are
treated as “Don’t Care.” Once a bank has been pre-
charged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued
to that bank.
Figure 31: PRECHARGE Command
Power-down (CKE Not Active)
Unlike SDR SDRAMs, DDR SDRAMs require CKE to
be active at all times an access is in progress, from the
issuing of a READ or WRITE command until comple-
tion of the access. Thus a clock suspend is not sup-
ported. For READs, an access completion is defined
when the Read Postamble is satisfied; for WRITEs, an
access completion is defined when the Write Recovery
time (tWR) is satisfied.
Power-down as shown in Figure 32 on page 41, is
entered when CKE is registered LOW and all Table 7
(page 41) criteria are met. If power-down occurs when
all banks are idle, this mode is referred to as precharge
power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as
active power-down. Entering power-down deactivates
the input and output buffers, excluding CK, CK#, and
CKE. For maximum power savings, the DLL is frozen
during precharge power-down mode. Exiting power-
down requires the device to be at the same voltage and
frequency as when it entered power-down. However,
power-down duration is limited by the refresh require-
ments of the device (tREFC).
While in power-down, CKE LOW and a stable clock
signal must be maintained at the inputs of the DDR
SDRAM, while all other input signals are “Don’t Care.”
The power-down state is synchronously exited when
CKE is registered HIGH (in conjunction with a NOP or
DESELECT command). A valid executable command
may be applied one clock cycle later.
CS#
WE#
CAS#
RAS#
CKE
A10
BA0,1
HIGH
ALL BANKS
ONE BANK
BA
A0–A9, A11, A12
CK
CK#
BA = Bank Address (if A10 is LOW;
otherwise “Don’t Care”)
DON’T CARE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT46V32M16BN-5BLIT | 32M X 16 DDR DRAM, 0.7 ns, PBGA60 |
| MT46V32M81AZ4-6T:G | 32M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| MT47H128M8HV-187ELIT:E | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| MT47H128M8HQ-187ELAT:E | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| MT48LC2M32B1TG-7 | 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V32M16TG-75L | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M16TG-75Z | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M16TG-75ZL | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
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