![](http://datasheet.mmic.net.cn/180000/MT46V32M16TG-75ELIT_datasheet_11334047/MT46V32M16TG-75ELIT_74.png)
512Mb: x4, x8, x16
DDR SDRAM
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN
74
2000 Micron Technology, Inc. All rights reserved.
Figure 47: Auto Refresh Mode
NOTE:
1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row Address, BA = Bank Address.
2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be
active during clock positive transitions.
3. NOP or COMMAND INHIBIT are the only commands allowed until after tRFC time, CKE must be active during clock posi-
tive transitions.
4. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e., must precharge all
active banks).
5. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
6. The second AUTO REFRESH is not required and is only shown as an example of two back-to-back AUTO REFRESH com-
mands.
CK
CK#
COMMAND1
NOP2
VALID
NOP 2
NOP2
PRE
CKE
RA
A0-A9,
A11, A121
A101
BA0, BA11
Bank(s)4
BA
AR
NOP2, 3
AR6
NOP2, 3
ACT
NOP2
ONE BANK
ALL BANKS
CK
tCH
tCL
tIS
tIH
tIS
tIH
RA
DQ5
DM5
DQS5
tRFC5
tRP
tRFC
T0
T1
T2
T3
T4
Ta0
Tb0
Ta1
Tb1
Tb2
DON’T CARE
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-5B
-6/-6T
-75E/75Z
-75
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS
tCH
0.45 0.55 0.45 0.55 0.45
0.55 0.45 0.55
tCK
tCL
0.45 0.55 0.45 0.55 0.45
0.55 0.45 0.55
tCK
tCK (3)
5
7.5
NANA
NA
NANA
ns
tCK (2.5)
6
13
6
13
7.5
13
7.5
13
ns
tCK (2)
7.5
13
7.5
13
7.5
13
10
13
ns
tIH
F
.75
.90
ns
tIS
F
.75
.90
ns
tIH
S
.75
0.8
1
ns
tIS
S
.75
0.8
1
ns
tRFC
75
72
75
ns
tRP
15
20
ns
-5B
-6/-6T
-75E/75Z
-75
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS