- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄224505 > MT46V32M16TG-75ELIT 32M X 16 DDR DRAM, 0.75 ns, PDSO66 PDF資料下載
參數(shù)資料
| 型號(hào)： | MT46V32M16TG-75ELIT |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP-66 |
| 文件頁(yè)數(shù)： | 75/82頁(yè) |
| 文件大?。?/td> | 2855K |
| 代理商： | MT46V32M16TG-75ELIT |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)當(dāng)前第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)
512Mb: x4, x8, x16
DDR SDRAM
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN
77
2000 Micron Technology, Inc. All rights reserved.
Figure 50: Bank Read - With Auto Precharge
NOTE:
1. DOn = data-out from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = Row Address, BA = Bank Address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these times.
6. The READ command can only be applied at T3 if tRAP is satisfied at T3.
7. tRP starts only after tRAS has been satisfied.
8. Refer to Figure 40 on page 67, Figure 41 on page 68, and Figure 42 on page 69 for detailed DQS and DQ timing.
CK
CK#
CKE
A10
BA0, BA1
tCK
tCH
tCL
tIS
tIH
tIS
tIH
IS
IH
RA
tRC
tRP7
CL = 2
DM
T0
T1
T2
T3
T4
T5
T5n
T6n
T6
T7
T8
DQ1
DQS
Case 1: tAC (MIN) and tDQSCK (MIN)
Case 2: tAC (MAX) and tDQSCK (MAX)
DQ1
DQS
tRPRE
tRPST
tDQSCK (MIN)
tDQSCK (MAX)
tAC (MIN)
tLZ (MIN)
DO
n
tHZ (MAX)
tAC (MAX)
DO
n
NOP5
COMMAND4
3
ACT
RA
Col n
READ2,6
NOP5
Bank x
RA
Bank x
ACT
Bank x
NOP5
DON’T CARE
TRANSITIONING DATA
tRAS
tLZ(MIN)
tRCD, tRAP6
x8: A12
x16: A11, A12
x4: A0–A9, A11, A12
x8: A0–A9, A11
x16: A0–A9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT46V32M16BN-5BLIT | 32M X 16 DDR DRAM, 0.7 ns, PBGA60 |
| MT46V32M81AZ4-6T:G | 32M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| MT47H128M8HV-187ELIT:E | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| MT47H128M8HQ-187ELAT:E | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| MT48LC2M32B1TG-7 | 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V32M16TG-75L | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M16TG-75Z | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M16TG-75ZL | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。