參數(shù)資料
型號(hào): MT9074
廠商: Mitel Networks Corporation
英文描述: T1/E1/J1 Single Chip Transceiver
中文描述: T1/E1/J1收發(fā)單芯片收發(fā)器
文件頁(yè)數(shù): 101/122頁(yè)
文件大小: 372K
代理商: MT9074
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Advance Information
MT9074
101
Bit
Name
Functional Description
7
INTGEN
Interrupt Generated. Set to 1 when an interrupt (in conjunction with the Interrupt
Mask Register) has been generated by the HDLC. This is an asynchronous event.
It is reset when the interrupt Register is read.
6
Idle Chan
Idle Channel. Set to a 1 when an idle Channel state (15 or more ones) has been
detected at the receiver. This is an asynchronous event. On power reset, this may
be 1 if the clock (RXC) was not operating. Status becomes valid after the first 15
bits or the first zero is received.
5 - 4
RQ9, RQ8
Byte Status bits from RX FIFO. These bits determine the status of the byte to be
read from RX FIFO as follows:
RQ9 RQ8 Byte Status
0 0 Packet Byte
0 1 First Byte
1 0 Last byte of a good packet.
1 1 Last byte of a bad packet.
3 - 2
TxSTAT2-1
These bits determine the status of the TX FIFO as follows:
TxSTAT2 TxSTAT1 TX FIFO Status
0 0 TX FIFO full up to the selected status level or more.
0 1 The number of bytes in the TX FIFO has reached or
exceeded the selected interrupt threshold level.
1 0 TX FIFO empty.
1 1 The number of bytes in the TX FIFO is less than the
selected interrupt threshold level.
1 - 0
RxSTAT2 - 1
These bits determine the status of the RX FIFO as follows:
RxSTAT2 RxSTAT1 RX FIFO Status
0 0 RX FIFO empty
0 1 The number of bytes in the RX FIFO is less
than the interrupt threshold level.
1 0 RX FIFO full.
1 1 The number of bytes in the RX FIFO has reached or
exceeded the interrupt threshold level.
Table 145 - HDLC Status Register
(Page B & C Address 14H)
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