參數(shù)資料
型號： MT9074
廠商： Mitel Networks Corporation
英文描述： T1/E1/J1 Single Chip Transceiver
中文描述： T1/E1/J1收發(fā)單芯片收發(fā)器
文件頁數(shù)： 84/122頁
文件大?。?/td> 372K
代理商： MT9074
MT9074
Advance Information
84
1
RAIS
Remote Alarm Indication Status
.
If one, there is currently a remote
alarm condition (i.e., received A bit
is one). If zero, normal operation.
Updated on a non-frame alignment
frame basis.
0
RCRS
RAI and Continuous CRC Error
Status
. If one, there is currently an
RAI and continuous CRC error
condition.
If
operation.
Updated
multiframe basis.
zero,
normal
on
a
Bit
Name
Functional Description
Table 104 - Alarm Status Word 1
(Page 3, Address 11H) (continued) (E1)
Bit
Name
Functional Description
7
1SEC
One Second Timer Status
. This bit
changes state once every 0.5 second
and is synchronous with the 2SEC
timer.
6
2SEC
Two Second Timer Status
. This bit
changes state once every second and
is synchronous with the 1SEC timer.
5
400T
400 msec. Timer Status
. This bit
changes state when the 400 msec.
CRC-4 multiframe alignment timer
expires.
4
--
Unused.
3
CALN
CRC-4 Alignment.
This bit changes
state every msec. When CRC-4
multiframe
alignment
achieved state changes of this bit are
synchronous with the receive CRC-4
synchronization signal.
has
been
2
KLVE
Keep Alive.
This bit is high when the
AIS status bit has been high for at least
100msec. This bit will be low when AIS
goes low (I.431).
1
T1
Timer One
. This bit will be high upon
loss of terminal frame synchronization
persisting for 100 msec. This bit shall
be low when T2 becomes high. Refer
to I.431 Section 5.9.2.2.3.
0
T2
Timer Two.
This bit will be high when
the MT9074 acquires terminal frame
synchronization persisting for 10 msec.
This bit shall be low when non-normal
operational frames are received. I.431
Section 5.9.2.2.3.
Table 105 - Timer Status Word
(Page 3, Address 12H) (E1)
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參數(shù)描述
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