參數(shù)資料
型號： MT9074
廠商： Mitel Networks Corporation
英文描述： T1/E1/J1 Single Chip Transceiver
中文描述： T1/E1/J1收發(fā)單芯片收發(fā)器
文件頁數(shù)： 61/122頁
文件大?。?/td> 372K
代理商： MT9074
Advance Information
MT9074
61
Bit
Name
Functional Description
7
TFSYNI
Terminal Frame Synchronization
Interrupt
. When unmasked this
interrupt bit goes high whenever a
change of state of terminal frame
synchronization condition exists.
Reading this register clears this bit.
6
MFSYNI
Multiframe
Interrupt
. When unmasked this
interrupt bit goes high whenever a
change of state of multiframe
synchronization condition exists.
Reading this register clears this bit.
Synchronization
5
- - -
Unused
.
4
AISI
Alarm Indication Signal Interrupt
.
When unmasked this interrupt bit
goes high whenever a change of
state of received all ones condition
exists. Reading this register clears
this bit.
3
LOSI
Loss of Signal Interrupt.
When
unmasked this interrupt bit goes
high whenever a change of state of
loss of signal (either analog - signal
40 dB below nominal or digital - 192
consecutive 0’s received) condition
exists. Reading this register clears
this bit.
2
SEI
Severely Errored Frame Interrupt
.
When unmasked this interrupt bit
goes high whenever a sequence of
2 framing errors out of 6 occurs.
Reading this register clears this bit.
1
TxSLPI
Transmit SLIP Interrupt
. When
unmasked this interrupt goes high
whenever a controlled frame slip
occurs in the transmit elastic buffer.
Reading this register clears this bit.
0
RxSLPI
Receive SLIP Interrupt
. When
unmasked this interrupt bit goes
high whenever a controlled frame
slip occurs in the receive elastic
buffer. Reading this register clears
this bit.
Table 66 - Interrupt Word Zero
(Page 4, Address 1BH) (T1)
Bit
Name
Functional Description
7
FEI
Framing Bit Error Interrupt.
When
unmasked this interrupt bit goes high
whenever an erroneous framing bit is
detected (provided the circuit is in
terminal frame sync). Reading this
register clears this bit.
6
CRCI
CRC-6
unmasked this interrupt bit goes high
whenever a local CRC-6 error occurs.
Reading this register clears this bit.
Error
Interrupt
.
When
5
YELI
Yellow
unmasked this interrupt bit goes high
upon detection of a yellow alarm.
Reading this register clears this bit.
Alarm
Interrupt
.
When
4
COFAI
Change
Interrupt
.
interrupt bit goes high whenever a
change of frame alignment occurs
after a reframe. Reading this register
clears this bit.
of
When
Frame
Alignment
unmasked
this
3
BPVI
Bipolar Violation Interrupt
. When
unmasked this interrupt bit goes high
whenever
a
(excluding
B8ZS
encountered. Reading this register
clears this bit.
bipolar
violation
encoding)
is
2
PRBSI
Psuedo Random Bit Sequence
Error Interrupt
. When unmasked this
interrupt bit goes high upon detection
of an error with a channel selected for
PRBS testing. Reading this register
clears this bit.
1
PDVI
Pulse Density Violation Interrupt
.
When unmasked this interrupt bit goes
high whenever in the absence of B8ZS
coding a sequence of 16 consecutive
zeros is received on the line, or the
incoming pulse density is less than N
ones in a time frame of 8(N+1) where
N = 1 to 23. In the case of B8ZS
coding, the interrupt is set upon
detection of 8 consecutive zeros.
Reading this register clears this bit.
0
- - -
Unused
.
Table 67 - Interrupt Word One
(Page 4, Address 1CH) (T1)
相關(guān)PDF資料
PDF描述
MT9074AL T1/E1/J1 Single Chip Transceiver
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MT9074 T1/E1/J1 Single Chip Transceiver(T1/E1/J1單片收發(fā)器)
MT9075B E1 Single Chip Transceiver
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參數(shù)描述
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