參數(shù)資料
型號： MT9074AL
廠商： Mitel Networks Corporation
英文描述： T1/E1/J1 Single Chip Transceiver
中文描述： T1/E1/J1收發(fā)單芯片收發(fā)器
文件頁數(shù)： 104/122頁
文件大小： 372K
代理商： MT9074AL
MT9074
Advance Information
104
Bit
Name
Functional Description
7-
0s
TxCNT
7-0
Transmit Byte Count Register.
The
Transmit
Byte
indicating the length of the packet
about to be transmitted. When this
register reaches the count of one, the
next write to the Tx FIFO will be tagged
as an end of packet byte. The counter
decrements at the end of the write to
the Tx FIFO. If the Cycle bit of Control
Register 2 is set high, the counter will
cycle through the programmed value
continuously.
Count
Register
Table 151 - Transmit Byte Count Register
(Page B & C, Address 1AH)
Bit
Name
Functional Description
7
HRST
HDLC Reset.
When this bit is set
to one, the HDLC will be reset.
This is similar to RESET being
applied, the only difference being
that this bit will not be reset. This
bit can only be reset by writing a
zero twice to this location or
applying RESET.
6
RTLOOP
RT Loopback.
When this bit is
high, receive to transmit HDLC
loopback
will
Receive data, including end of
packet
indication,
including flags or CRC, will be
written to the TX FIFO as well as
the
RX
FIFO.
transmitter is enabled, this data
will be transmitted as though
written by the microprocessor.
Both good and bad packets will
be looped back. Receive to
transmit loopback may also be
accomplished by reading the RX
FIFO using the microprocessor
and writing these bytes, with
appropriate tags, into the TX
FIFO.
be
activated.
but
not
When
the
5
RSV
Reserved
. Must be set to 0 for
normal operation.
4
RSV
Reserved
. Must be set to 0 for
normal operation.
Table 152 - HDLC Test Control Register
(Page B & C, Address 1BH)
3
CRCTST
CRC Remainder Test.
This bit
allows direct access to the CRC
Comparison
Register
receiver
through
interface. After testing is enabled,
serial data is clocked in until the
data aligns with the internal
comparison
(16
cycles) and then the clock is
stopped. The expected pattern is
F0B8 hex. Each bit of the CRC
can be corrupted to allow more
efficient testing.
in
the
the
serial
RXC
clock
2
FTST
FIFO Test.
This bit allows the
writing to the RX FIFO and
reading of the TX FIFO through
the microprocessor to allow
more efficient testing of the FIFO
status/interrupt functionality. This
is done by making a TX FIFO
write become a RX FIFO write
and a RX FIFO read become a
TX FIFO read. In addition, EOP/
FA and RQ8/RQ9 are re-defined
to be accessible (i.e. RX write
causes EOP/FA to go to RX fifo
input; TX read looks at output of
TX fifo through RQ8/RQ9 bits).
1
ARTST
Address Recognition Test.
This
bit allows direct access to the
Address Recognition Registers in
the receiver through the serial
interface to allow more efficient
testing. After address testing is
enabled, serial data is clocked in
until the data aligns with the
internal address comparison (16
RXc clock cycles) and then clock
is stopped.
0
HLOOP
TR
transmit
loopback will be activated. The
packetized transmit data will be
looped back to the receive input.
RXEN and TXEN bits must also
be enabled.
Loopback.
to
When
receive
high,
HDLC
Bit
Name
Functional Description
Table 152 - HDLC Test Control Register
(Page B & C, Address 1BH)
相關(guān)PDF資料
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