參數(shù)資料
型號： MT9074AL
廠商： Mitel Networks Corporation
英文描述： T1/E1/J1 Single Chip Transceiver
中文描述： T1/E1/J1收發(fā)單芯片收發(fā)器
文件頁數(shù)： 99/122頁
文件大?。?/td> 372K
代理商： MT9074AL
Advance Information
MT9074
99
Bit
Name
Functional Description
7 - 2
ADR16-11
Address 16 - 11. A six bit
address used for comparison
with the first byte of the received
address. ADR16 is MSB.
1
ADR10
Address 10. This bit is used in
address comparison if a seven
bit address is being checked for
(control bit four of control register
2 is set).
0
A1EN
First
Enable. When this bit is high, the
above six (or seven) bit address
is used in the comparison of the
first address byte.
If address recognition is enabled,
any packet failing the address
comparison will not be stored in
the RX FIFO. A1EN must be high
for All-call (1111111) address
recognition
for
address. When this bit is low, this
bit mask is ignored in address
comparison
Address
Comparison
single
byte
Table 140 - HDLC Address Recognition Register
1
(Page B & C, Address 10H)
Bit
Name
Functional Description
7 - 1 ADR26-20 Address 26 - 20. A seven bit
address used for comparison with
the second byte of the received
address. ADR26 is MSB. This
mask is ignored (as well as first
byte mask) if all call address
(1111111) is received.
0
A2EN
Second
Enable. When this bit is set high,
the above seven bit address is
used in the comparison of the
second address byte.
If address recognition is enabled,
any packet failing the address
comparison will not be stored in
the RX FIFO. A2EN must be high
for All-call address recognition.
When this bit is low, this bit mask
is ignored in address comparison
Address
Comparison
Table 141 - HDLC Address Recognition
Register2 (Page B & C, Address 11H)
Bit
Name
Functional Description
7 - 0 BIT7-0 This eight bit word is tagged with the
two status bits from the control register
1 (EOP and FA), and the resulting 10
bit word is written to the TX FIFO. The
FIFO
status
immediately after a write or read
occurs. It is updated after the data has
settled and the transfer to the last
available position has finished.
is
not
changed
Table 142 - TX FIFO Write Register
(Page B & C, Address 12H)
Bit
Name
Functional Description
7 - 0 BIT7-0 This is the received data byte read
from the RX FIFO. The status bits of
this byte can be read from the status
register. The FIFO status is not
changed immediately when a write or
read occurs. It is updated after the
data has settled and the transfer to the
last available position has finished.
Table 143 - RX FIFO Read Register
(Page B & C, Address 12H)
相關PDF資料
PDF描述
MT9074AP T1/E1/J1 Single Chip Transceiver
MT9074 T1/E1/J1 Single Chip Transceiver(T1/E1/J1單片收發(fā)器)
MT9075B E1 Single Chip Transceiver
MT9075B E1 Single Chip Transceiver(E1單片收發(fā)器)
MT9075 E1 Single Chip Transceiver
相關代理商/技術參數(shù)
參數(shù)描述
MT9074AL1 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 100MQFP - Trays
MT9074AP 制造商:Microsemi Corporation 功能描述:
MT9074AP1 制造商:Microsemi Corporation 功能描述:T1/E1/J1 SGLE CHIP XSCR 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 68PLCC - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TXRX SGL T1/E1 68PLCC 制造商:Microsemi Corporation 功能描述:IC TXRX SGL T1/E1 68PLCC
MT9074APR 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 Single Chip Transceiver
MT9074APR1 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 68PLCC - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 5V 68PLCC - Tape and Reel
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