- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄383644 > MT9074AL (Mitel Networks Corporation) T1/E1/J1 Single Chip Transceiver PDF資料下載
參數(shù)資料
| 型號(hào)： | MT9074AL |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | T1/E1/J1 Single Chip Transceiver |
| 中文描述： | T1/E1/J1收發(fā)單芯片收發(fā)器 |
| 文件頁(yè)數(shù)： | 29/122頁(yè) |
| 文件大?。?/td> | 372K |
| 代理商： | MT9074AL |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)當(dāng)前第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)
Advance Information
MT9074
29
system the receive data is in phase with the E1.5o
clock, the C4b clock is phase-locked to the E1.5o
clock, and the read and write positions of the slip
buffer will remain fixed with respect to each other.
In a multi-trunk slave or loop-timed system (i.e.,
PABX application) a single trunk will be chosen as a
network synchronizer, which will function as
described in the previous paragraph. The remaining
trunks will use the system timing derived from the
synchronizer to clock data out of their slip buffers.
Even though the PCM 30 signals from the network
are synchronous to each other, due to multiplexing,
transmission impairments and route diversity, these
signals may jitter or wander with respect to the
synchronizing trunk signal. Therefore, the E1.5o
clocks of non-synchronizer trunks may wander with
respect to the C1.50 clock of the synchronizer and
the system bus.
Network standards state that, within limits, trunk
interfaces must be able to receive error-free data in
the presence of jitter and wander (refer to network
requirements for jitter and wander tolerance). The
MT9074 will allow a maximum of 26 channels (208
UI, unit intervals) of wander and low frequency jitter
before a frame slip will occur.
The minimum delay through the receive slip buffer is
approximately two channels and the maximum delay
is approximately 60 channels (see Figure 14).
When the C4b and the E1.5o clocks are not phase-
locked, the rate at which data is being written into the
slip buffer from the PCM 30 side may differ from the
rate at which it is being read out onto the ST-BUS. If
this situation persists, the delay limits stated in the
previous paragraph will be violated and the slip
buffer will perform a controlled frame slip. That is, the
buffer pointers will be automatically adjusted so that
a full PCM 30 frame is either repeated or lost. All
frame slips occur on PCM 30 frame boundaries.
Two status bits, RSLIP and RSLPD (page03H,
address13H) give indication of a slip occurrence and
direction. RSLIP changes state in the event of a slip.
If RSLPD=0, the slip buffer has overflowed and a
frame was lost; if RSLPD=1, an underflow condition
occurred and a frame was repeated. A maskable
interrupt SLPI (page 01H, address 1BH) is also
provided.
Figure 14 illustrates the relationship between the
read and write pointers of the receive slip buffer.
Measuring clockwise from the write pointer, if the
read pointer comes within two channels of the write
pointer a frame slip will occur, which will put the read
pointer 34 channels from the write pointer.
Conversely, if the read pointer moves more than 60
Figure 13 - Read and write pointers in the receive slip buffers
Write
Pointer
0 uS
249 uS
32 uS
188 uS
62 uS
157 uS
512 Bit
Elastic
Store
92 uS
92 uS
Wander Tolerance
Read Pointer
Read Pointer
Read Pointer
Read Pointer
Frame 0
Frame 1
Frame 0
Frame 1
Frame 0
Frame 1
XXX
XXX
XXX
XXX
Write Vectors
Read Vectors
Minimum Delay
Read Vectors - Maximum Delay
124 uS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9074AP | T1/E1/J1 Single Chip Transceiver |
| MT9074 | T1/E1/J1 Single Chip Transceiver(T1/E1/J1單片收發(fā)器) |
| MT9075B | E1 Single Chip Transceiver |
| MT9075B | E1 Single Chip Transceiver(E1單片收發(fā)器) |
| MT9075 | E1 Single Chip Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9074AL1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 100MQFP - Trays |
| MT9074AP | 制造商:Microsemi Corporation 功能描述: |
| MT9074AP1 | 制造商:Microsemi Corporation 功能描述:T1/E1/J1 SGLE CHIP XSCR 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 68PLCC - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TXRX SGL T1/E1 68PLCC 制造商:Microsemi Corporation 功能描述:IC TXRX SGL T1/E1 68PLCC |
| MT9074APR | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:T1/E1/J1 Single Chip Transceiver |
| MT9074APR1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 68PLCC - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 5V 68PLCC - Tape and Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。