參數(shù)資料
型號(hào)： MT9074AL
廠商： Mitel Networks Corporation
英文描述： T1/E1/J1 Single Chip Transceiver
中文描述： T1/E1/J1收發(fā)單芯片收發(fā)器
文件頁(yè)數(shù)： 46/122頁(yè)
文件大?。?/td> 372K
代理商： MT9074AL
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MT9074
Advance Information
46
Bit
Name
Functional Description
7
RxB8ZS
Receive B8ZS Enable
. If one,
receive
B8ZS
enabled.
decoding
is
6
MLBK
Metallic Loopback
. If one, then
RRTIP/RRING
directly to TTIP and TRING
respectively. If zero, this feature is
disabled. Set the transmit line
build out to -7.5dB when metallic
loopback is enabled.
are
connected
5
TxB8ZS
Transmit B8ZS Enable
. If one, all
zero octets are substituted with
B8ZS codes.
4
FBS
Forced Bit Stuffing
. If set any
transmit DS0 channel containing
all zeros has bit 7 forced high.
3
DLBK
Digital Loopback
. If one, the
digital stream to the transmit LIU
is looped back in place of the
digital output of the receive LIU.
Data coming out of DSTo will be a
delayed version of DSTi. If zero,
this feature is disabled.
2
RLBK
Remote Loopback
. If one, all
time slots received on RRTIP/
RRING are connected to TTIP/
TRING on the DS1 side of the
MT9074. If zero, this feature is
disabled.
1
SLBK
ST-BUS Loopback
. If one, all
time slots of DSTi are connected
to DSTo on the ST-BUS side of the
MT9074. If zero, this feature is
disabled. See Loopbacks section.
Table 26 - Coding and Loopback Control Word
(T1)(Page 1, Address 15H)
0
PLBK
Payload Loopback
. If one, all
time slots received on RTIP/
RRING are connected to TTIP/
TRING on the ST-BUS side of the
MT9074. If zero, this feature is
disabled. If receive robbed bit
signaling data is to be included in
the looped data, then the control
bit RBEn (Page 1 Address 14H,
Bit 5) must be set low, otherwise
transmit signaling data will be
placed into the LSB of each
timeslot every sixth frame. Setting
all Clear Channel control bits high
(Bit 0 in the Per Time Slot Control
words - Pages 7 and 8 Address
10H to IFH inclusive) has the
same effect as setting control bit
RBEn low.
Bit
Name
Functional Description
7-0
- - -
Unused
Table 27 - Reserved (T1)
(Page 1, Address 16H)
Bit
Name
Functional Description
7-0
TxSD7-0
Transmit Set Delay Bits 7-0.
Writing to this register forces a one
time setting of the delay through the
transmit slip buffer. Delay is defined
as the time interval between the
write of the transmit STBUS channel
containing DS1 timeslot 1 and its
subsequent read. Delay is modified
by moving the position of the
internally generated DS1 frame
boundary.Delay (when set) will
always be less than 1 frame
(125uS). This register must be
programmed with a non-zero value
(such as 0FH).
Table 28 - Transmit Elastic Buffer Set Delay
Word (T1) (Page 1, Address 17H)
Bit
Name
Functional Description
Table 26 - Coding and Loopback Control Word
(T1)(Page 1, Address 15H)
相關(guān)PDF資料
PDF描述
MT9074AP T1/E1/J1 Single Chip Transceiver
MT9074 T1/E1/J1 Single Chip Transceiver(T1/E1/J1單片收發(fā)器)
MT9075B E1 Single Chip Transceiver
MT9075B E1 Single Chip Transceiver(E1單片收發(fā)器)
MT9075 E1 Single Chip Transceiver
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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MT9074APR 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 Single Chip Transceiver
MT9074APR1 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 68PLCC - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 5V 68PLCC - Tape and Reel
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