參數(shù)資料
型號(hào)： MT9076
廠商： Mitel Networks Corporation
英文描述： T1/E1/J1 3.3V Single Chip Transceiver(T1/E1/J1 3.3V 單片收發(fā)器)
中文描述： T1/E1/J1收發(fā)3.3V的單芯片收發(fā)器（T1/E1/J1收發(fā)3.3單片收發(fā)器）
文件頁數(shù)： 127/162頁
文件大?。?/td> 427K
代理商： MT9076
Preliminary Information
MT9076
123
Bit
Name
Functional Description
7
HDLC0I
HDLC0 Interrupt.
Whenever an unmasked HDLC0 interrupt occurs, this bit goes high.
Reading this register clears this bit.
6
HDLC1I
HDLC1 Interrupt.
Whenever an unmasked HDLC1 interrupt occurs, this bit goes high.
Reading this register clears this bit.
5
HDLC2I
HDLC2 Interrupt.
Whenever an unmasked HDLC2 interrupt occurs, this bit goes high.
Reading this register clears this bit.
4
JAI
Jitter Attenuator Error Interrupt
. Whenever an unmasked JAI interrupt occurs.
If jitter attenuator FIFO comes within four bytes of an overflow or underflow, this bit goes
high. Reading this register clears this bit.
3
1SECI
One Second Status Interrupt.
When unmasked this interrupt bit goes high whenever the
1SEC status bit (page 3 address 12H bit 7) goes from low to high. Reading this register
clears this bit.
2
5SECI
Five Second Status Interrupt
. When unmasked this interrupt bit goes high whenever the 5
SEC status bit goes from low to high. Reading this register clears this bit.
1
RCRI
RCRI Interrupt.
Whenever an unmasked RCRI interrupt occurs. If remote alarm and CRC
error occur this bit goes high. Reading this register clears this bit.
0
SIGI
signaling Interrupt
. When unmasked this interrupt bit goes high whenever a change of
state (optionally debounced - see DBEn in the Data Link, signaling Control Word) is
detected in the signaling bits (AB or ABCD) pattern. Reading this register clears this bit.
Table 147 - Interrupt Word Three
(Page 4, Address 1EH) (E1)
Bit
Name
Functional Description
7
FERROL
Errored Frame Alignment Signal Counter Overflow Latch
. This bit is set when
the errored frame alignment signal counter overflows. It is cleared after being read.
6
CRCOL
CRC Error Counter Overflow Latch
. This bit is set when the crc error counter
overflows. It is cleared after being read.
5
FEBEOL
E bit Counter Overflow Latch.
This bit is set when E bit counter overflows. It is
cleared after being read.
4
- - -
3
LCVOL
Line Code Violation Counter Overflow Latch
. This bit is set when the line code
violation counter overflows. It is cleared after being read.
2
PRBSOL
Pseudo Random Bit Sequence Error Counter Overflow Latch
. This bit is set
when the PRBS error counter overflows. It is cleared after being read.
1
PRBSMFOL
Pseudo Random Bit Sequence Multiframe Counter Overflow Latch.
This bit is
set when the multiframe counter attached to the PRBS error counter overflows. It is
cleared after being read
0
- - -
Unused.
Table 148 - Overflow Reporting Latch
(Page 4, Address 1FH) (E1)
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT9076AB 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:T1/E1/J1 3.3V Single Chip Transceiver
MT9076AP 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:T1/E1/J1 3.3V Single Chip Transceiver
MT9076B 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 3.3 V Single Chip Transceiver
MT9076BB 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays
MT9076BB1 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays
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