參數(shù)資料
型號： MT9076
廠商： Mitel Networks Corporation
英文描述： T1/E1/J1 3.3V Single Chip Transceiver(T1/E1/J1 3.3V 單片收發(fā)器)
中文描述： T1/E1/J1收發(fā)3.3V的單芯片收發(fā)器（T1/E1/J1收發(fā)3.3單片收發(fā)器）
文件頁數(shù)： 5/162頁
文件大?。?/td> 427K
代理商： MT9076
Preliminary Information
MT9076
5
42
17
RxMF/
TxFP
Receive Multiframe Boundary / Transmit Frame Boundary (5V tolerant Output).
If
the control bit Tx8KEN (page 02H address 10H bit 2) is low, this negative output pulse
delimits the received multiframe boundary. The next frame output on the data stream
(DSTo) is basic frame zero on the T1 or PCM 30 link. In E1 mode this receive
multiframe signal can be related to either the receive CRC multiframe (page 01H,
address 17H, bit 6, MFSEL=1) or the receive signaling multiframe (MFSEL=0). If the
control bit Tx8KEN is set high, this positive output pulse delimits the frame boundary
(the first bit transmit in the frame) for the digital output stream on pins TXA and TXB.
43
18
BS/LS
Bus/Line Syncronization Mode Selection (5V tolerant Input)
. If high, C4b and F0b
will be inputs; if low, C4b and F0b will be outputs.
44
22
Exclk
2.048 MHz in E1 mode or 1.544MHz in T1 mode, Extracted Clock (5V tolerant
Output).
The clock extracted from the received signal and used internally to clock in
data received on RTIP and RRING.
45
23
C4b
4.096 MHz System Clock (5V tolerant Input/Output).
C4b is the clock for the ST-BUS
sections and transmit serial PCM data of the MT9076. In the free-run (S/FR/Exclki=0) or
line synchronous mode (S/FR/Exclki=1 and BS/LS=0) this signal is an output, while in
bus synchronous mode (S/FR/Exclki=1 and BS/LS=1) this signal is an input clock.
46
24
F0b
Frame Pulse (5V tolerant Input/Output).
This is the ST-BUS frame synchronization
signal, which delimits the 32 channel frame of CSTi, CSTo, DSTi, DSTo and the
PCM30 link. In the free-run (S/FR/Exclki=0) or line synchronous mode (S/FR/Exclki=1
and BS/LS=0) this signal is an output, while in bus synchronous mode (S/FR/Exclki=1
and BS/LS=1) this signal is an input.
47
25
RxFP
Receive Frame Pulse/Receive CCS Clock (5V tolerant Output).
An 8kHz pulse
signal, which is low for one extracted clock period. This signal is synchronized to the
receive DS1 or PCM 30 basic frame boundary.
48
26
IC1
Internal Connection.
Must be left open for normal operation.
49
27
V
SS2
V
DD2
VDD
ATx
TTIP
TRING
Negative Power Supply.
Digital ground.
50
28
Positive Power Supply.
Digital supply (+3.3V
±
5%).
Transmit Analog Power Supply.
Analog supply for the LIU transmitter (+3.3V
±
5%).
51
29
52
53
30
31
Transmit TIP and RING(Output).
Differential outputs for the transmit line signal - must
be transformer coupled (See Figure 6).
54
32
GND
ATx
Tdi
Transmit Analog Ground .
Analog ground for the LIU transmitter.
55
33
IEEE 1149.1a Test Data Input (3V Input).
If not used, this pin should be pulled high.
56
34
Tdo
IEEE 1149.1a Test Data Output (5V tolerant Output).
If not used, this pin should be
left unconnected.
57
35
Tms
IEEE 1149.1a Test Mode Selection (3V Input)
. If not used, this pin should be pulled
high.
58
36
Tclk
IEEE 1149.1a Test Clock Signal (3V Input).
If not used, this pin should be pulled high.
59
37
Trst
IEEE 1149.1a Reset Signal (3V Input).
If not used, this pin should be held low.
60
38
TxAO
Transmit All Ones (Input).
High - TTIP, TRING will transmit data normally. Low - TTIP,
TRING will transmit an all ones signal.
Pin Description (continued)
Pin #
Name
Description
PLCC LQFP
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT9076AB 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:T1/E1/J1 3.3V Single Chip Transceiver
MT9076AP 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:T1/E1/J1 3.3V Single Chip Transceiver
MT9076B 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 3.3 V Single Chip Transceiver
MT9076BB 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays
MT9076BB1 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays
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