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參數(shù)資料
| 型號(hào)： | ORSO42G5-3BMN484C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 104/153頁(yè) |
| 文件大小： | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPGAM |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
54
There are N x 3 (N = 48) bytes of TOH per row and there are a total of 9 rows in a SONET frame. In cell mode, the
rest of the bytes in each row after the TOH bytes are lled by cells. The rst byte in a cell is a Link Header (LH) byte.
At the end of each frame, there are pad bytes if required.
An important function of the payload block is the grouping of bytes together to be presented to the scramble logic.
Due to the insertion of the LH byte in each cell, the total cell data are not divisible by 4 (4 bytes are sent per 77.76
MHz clock cycle). At the end of each row within a SONET frame, the payload block stops sending cell data and
indicates to the TOH block to insert the next row’s TOH bytes. At the end of the TOH byte transmission, the cell data
transmission is resumed.
At the end of a cell, the cell’s BIP-8 byte is inserted. The next cell’s Link Header byte (LH) immediately follows the
previous cell’s BIP-8 byte. The MSB of the LH byte is the link idle cell indicator bit. The payload block gets this bit
from the MSB of the rst word of a cell in the memory and inserts it into the LH byte for the appropriate cell. The
rest of the LH byte is the link sequence number. This number is incremented for each subsequent cell.
After all cells have been transmitted, the appropriate number of pad bytes are sent. At a link speed of 2.5 GHz,
there are 38,880 bytes (SPE + TOH) per frame. There are 1296 bytes of TOH and 37,584 bytes of SPE. For cell
data of 85 bytes this translates to 442 cells per frame and 14 pad bytes (# of cells per frame = # of bytes of SPE/#
of bytes in a cell).
Cell Mode Transmit Timing
Figure 40 shows the transmit clocks and recommended clocking scheme in cell mode. TCK156A, TCK157B can be
used as a 156 MHz clock source for SYSCLK156[A1, A2] and SYSCLK156[B1, B2] respectively. SYSCLK156[A1,
A2] and SYSCLK[B1, B2] are shared with the receive logic in cell mode.
Figure 40. Cell Mode Transmit Timing
When operating in the two-link CELL MODE, each OPC2 Block passes cells from FPGA to embedded core.
Depending upon the congured CELL SIZE, cell transfers will take a variable number of SYSCLK156 cycles to be
transmitted across the interface. Data are always transferred across a 40-bit bus (5 octets per clock cycle).
Figure 41 shows 16 clock cycles for a cell transfer this corresponds to a cell size of 79 octets. The two control sig-
nals in the gure are dened as:
cell_begin_ok: cell request signal from core to FPGA. It will be asserted every 20 or 16 clock cycles (depending
on cell size) when the core is ready to accept cells from FPGA.
OPC2
Payload
TXFIFO
FPGA
Cell Data
TCK78A
SYSCLK156[A:B][1:2]
Cell Valid
Backpressure Signal
TCK156A
or SYSCLK568
Block
TSYSCLKxx
Logic Common to Each Block
Cell Data
Cell Valid
Backpressure Signal
SDO_BP_8
OPC8_CELLVALID
OPC2_[A:B][1:2][39:0]
CELL_BEGIN_OK_[A:B][1:2]
OPC8 [159:0]
OPC2_[A:B][1:2]_CELLVALID
OPC2
OPC8 (ORSO82G5 only)
or
OPC8
(ORSO82G5
only)
相關(guān)PDF資料 |
PDF描述 |
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| ORT82G5-1FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| ORT82G5-2FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| VI-J4H-IW-F4 | CONVERTER MOD DC/DC 52V 100W |
| VI-J4H-IW-F3 | CONVERTER MOD DC/DC 52V 100W |
| ORT82G5-1FN680C | IC TRANCEIVERS FPSC 680FPBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORSO42G5-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORSO82G5 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
| ORSO82G5-1BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1BM680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1F680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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