- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11733 > ORSO42G5-3BMN484C (Lattice Semiconductor Corporation)IC TRANCEIVERS FPSC 680FPGAM PDF資料下載
參數(shù)資料
| 型號(hào)： | ORSO42G5-3BMN484C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 107/153頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPGAM |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | * |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)當(dāng)前第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
57
Link Header Detector
The Link Header detector determines when the next Link Header is coming in the frame and what the sequence
number contained within it should be. If the value of the cell sequence counter is not equal to the expected value,
then an error ag bit will set in the status registers and an error signal will be sent to the FPGA logic. The sequence
counter will increment to the next sequence number. The sequence count value is NOT updated with the incorrect
value, but is incremented each time a Link Header is received.
If excessive sequence errors are detected (three or more in a row), and the AUTO_REMOVE_[A:B] register bit is
set, then the corresponding link will be treated as not valid. The RX_LINK_GOOD status bit will go low indicating
the link is no longer receiving cells. If the AUTO_REMOVE_[A:B] register bit is not set, then the link is still valid
when excessive sequence errors are detected. An OOF condition will also trigger the link to be removed from ser-
vice if the AUTO_REMOVE_[A:B] register bit is set.
At startup or after a link has been removed from service (indicated by RX_LINK_GOOD going low), a link can be
rejoined into the group. This is performed via the per block REJOIN_[A:B] register bit. When rejoining a link the RX
FIFO will begin receiving cells. To cleanly rejoin a link into a group there are two methods to insure the RX FIFO
begins loading correctly. The rst method is to use the fast framing mode during the rejoin process. The can be
done by setting the FFRM_EN_xx for the links that need to be rejoined before setting the REJOIN_[A:B] bit.
The second method is to issue a block reset to clear the FIFO once all links that have been selected to be rejoined
are rejoined. This is done by rst setting the REJOIN_[A:B] bit. Once the RX_LINK_GOOD status bit is high for the
selected channels the GSWRST_[A:B] for the block should be set and cleared to reset the block. This method will
disturb trafc on all links in the block during the GSWRST_[A:B] reset time.
Once all of the links in a group are rejoined and the trafc is again owing the REJOIN_[A:B] bit should be cleared.
If this bit is not cleared, a link may drop out using the AUTO_REMOVE mode and the channel may be rejoined
incorrectly, causing errors on the entire group.
Receive FIFO
The main clock domain transfer for the data path is handled by the receive FIFO. A 16 x 161 FIFO is used in cell
mode. The FIFO is implemented as a dual-port memory which will support simultaneous reads and writes. The
receive FIFO block is written to at 77.76 MHz and read at 156 MHz.
The receive FIFO can allow for inter-link skew of about 800 ns (16 x 160 = 2560 bits, 400 ps per bit gives 1024 ns).
The 160 LSBs in the memory are received data and the 161st bit indicates the start of a new cell. The FIFO write
control logic indicates to the IPC, the start of a new frame of data. This signal will only be active for the A1 word of
a frame.
Once frame synchronization has occurred and the IPC has responded with a FIFO enable signal, data will be writ-
ten into the memory. Only the payload (cells) is written to the FIFO. The TOH bytes are not written into the FIFO.
The cell octets immediately following the A1A2 bytes will be always written to the top of the FIFO.
Once a full cell has been written to the memory, the write control logic will send a control signal to the IPC8 or IPC2
block which will start the process of reading data from the FIFO. The IPC will read one whole cell at a time from
each of the 8 FIFO blocks, if congured for the eight-link cell mode (ORSO82G5 only) or from each of 2 FIFO
blocks if congured for the two-link cell mode.
A FIFO occupancy counter generates a RX_FIFO_OVRUN indication to the register interface if it detects a FIFO
overow condition. The cell mode allows for alignment of all eight-links or alignment of two-links. Thus there will be
two IPC blocks for two pairs of channels per block.
Input Port Controllers
The input port controllers (IPCs) are the block responsible for “directing trafc” for the receive trafc ow. The block
diagrams for the 2-link and 8-link IPCs are shown in Figure 44. They provide the following essential functions.
Determining when cell data can be read from the FIFOs of the individual links.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ORT82G5-1FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| ORT82G5-2FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| VI-J4H-IW-F4 | CONVERTER MOD DC/DC 52V 100W |
| VI-J4H-IW-F3 | CONVERTER MOD DC/DC 52V 100W |
| ORT82G5-1FN680C | IC TRANCEIVERS FPSC 680FPBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORSO42G5-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORSO82G5 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
| ORSO82G5-1BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1BM680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1F680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。