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參數(shù)資料
| 型號(hào)： | ORSO42G5-3BMN484C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 68/153頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPGAM |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
21
The receiver section receives high-speed serial data at its differential CML input port. These data are fed to the
clock recovery section which generates a recovered clock and retimes the data. This means that the receive clocks
are asynchronous between channels. The retimed data are deserialized and presented as an 8-bit parallel data on
the output port. Two-phase receive byte clocks are available synchronous with the parallel words.
A fractional band-gap voltage generator is included on the design. An external resistor (3.32 kΩ ± 1%), connected
between the pins REXT and VSSREXT generates the bias currents within the chip. This resistor should be able to
handle at least 300 A.
32:8 MUX
The MUX block is responsible for converting 32 bits of data at 77.76 MHz to 8 bits of data at 311.04 MHz. It will
contain a small elastic store for clock domain transfer between the write clock from the FPGA to the divide-by-4
clock from the SERDES output clock (XCK311). It is recommended to use the clocking scheme shown later in
Figure 27, Figure 28 and Figure 29 to guarantee that this elastic store will not be overrun. The 32:8 MUX is also
responsible for producing the divide-by-4 clock from the SERDES output clock (XCK311) which is 311.04 MHz at a
line rate of 2.488 Gbps.
In the MUX block 32-bit data synchronous to the 77.76 MHz is multiplexed to LDOUTx[7:0] synchronous to the
311.04 MHz SERDES output clock. Parallel 32-bit data can be received directly from the FPGA logic (SERDES
only mode) or from the payload sub-block. Bit and byte alignment for the MUX block is shown in Figure 7.
Figure 7. Bit and Byte Alignment for MUX Block
The serialized data are available at the differential CML outputs to drive either an optical transmitter, coaxial media,
or circuit board/backplane. The transmitter’s CML output buffer is terminated on-chip by 86Ω to optimize the data
eye as well as to reduce the number of discrete components required. The differential output swing reaches a max-
imum of 1.2 VPP in the normal amplitude mode. A half amplitude mode can be selected via conguration register bit
HAMP_xx. Half amplitude mode can be used to reduce power dissipation when the transmission medium has min-
imal attenuation or for testing of the integrity (loss) of the physical medium.
A programmable preemphasis circuit is provided to boost the high frequencies in the transmit data signal to maxi-
mize the data eye opening at the far-end receiver. Preemphasis is particularly useful when the data are transmitted
over backplanes or low-quality coax cables which have a frequency-dependent amplitude loss. For example, for
FR4 material at 2.5 GHz, the attenuation compared to the 1.0 GHz value is about 3 dB. The attenuation is a result
of skin effect loss of the PCB conductor and the dielectric loss of the PCB substrate. This attenuation causes inter-
symbol interface which results in the closing of the data eye at the receiver.
Time
W
O
R
D
3
W
O
R
D
2
W
O
R
D
1
W
O
R
D
0
32:8
MUX
W
0
W
1
W
2
W
3
Bit and Byte alignment of the
32-bit 77MHz data LDIN[0:7]
through the 32:8 MUX block
to LDIN[0:7 is shown in the
diagram to the left.
7
0
7
0
31
0
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| ORT82G5-2FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| VI-J4H-IW-F4 | CONVERTER MOD DC/DC 52V 100W |
| VI-J4H-IW-F3 | CONVERTER MOD DC/DC 52V 100W |
| ORT82G5-1FN680C | IC TRANCEIVERS FPSC 680FPBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORSO42G5-EV | 功能描述:可編程邏輯 IC 開(kāi)發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORSO82G5 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
| ORSO82G5-1BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1BM680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1F680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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