- 您現(xiàn)在的位置：買(mǎi)賣IC網(wǎng) > PDF目錄11733 > ORSO42G5-3BMN484C (Lattice Semiconductor Corporation)IC TRANCEIVERS FPSC 680FPGAM PDF資料下載
參數(shù)資料
| 型號(hào)： | ORSO42G5-3BMN484C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 83/153頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPGAM |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | * |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)當(dāng)前第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
35
Section (B1) BIP-8 Calculator
The section BIP-8 B1 byte in a given STS-N frame contains the scrambled BIP value for all scrambled bytes of the
previous frame. Except for the A1,A2 and J0 section overhead bytes, all bytes in a frame are scrambled. The Sec-
tion (B1) BIP-8 is calculated as the even parity of all bits in the current STS-48 frame. This value is compared to the
Section Overhead B1 byte of the next frame. B1 error counters are available that monitors the number of B1 errors
on a per-channel basis. A B1 parity error ag is also generated as a software alarm bit.
Descrambler
The data from the framer is descrambled using the SONET/SDH standard generator polynomial 1 + x
6 + x7. The
descrambling is performed in parallel on each 32-bit word per channel, synchronized to the frame pulse and can be
disabled through the software register bit.
RDI (Remote Defect Indicator) Monitor
The line RDI (RDI-L) is monitored through bits 2-0 of the K2 byte. Within the 32-bit descrambled data, a pattern of
“110” on bits 26-24 will indicate a RDI-L status. RDI-L must be detected in two consecutive frames before an RDI
alarm register bit is set. If fast_frame_mode is enabled, then the RDI alarm register bit will be set if RDI-L is
detected in one frame.
Receive FIFO
Clock domain transfers and multi-link de-skew are one of the most critical parts of this device. The main clock
domain transfer for the datapath is handled by the receive FIFO. For each link, there are two FIFOs. A 24 x 33 FIFO
is used in SONET mode.
The use of the FIFO is controlled by conguration bits.
Data can be sent from the descrambler directly to the FPGA bypassing the alignment FIFO. Data from each
channel will have an associated clock (RWCKxx at 77.76 MHz). Each channel will also provide a FP and SPE
indicator along with the data. Descrambling can be inhibited through the DSCR_INH_xx control bit.
Data can be sent directly from the 8:32 DEMUX block to the FPGA bypassing the alignment FIFO and SONET
framer and descrambler. Data from each channel will have an associated clock. No SPE or FP indicator is pro-
vided with the data.
Receive FIFO in SONET mode
The receive FIFO used in SONET mode will allow for an inter-link skew of about 300 ns (24 x 32 = 768 bits, 400 ps
per bit gives 307 ns). The FIFO is written at 77.76 MHz and read at 77.76 MHz. Once frame synchronization has
occurred, the write control logic will cause data to be written to the memory. The write control block is required to
insure that the word containing the rst A1 byte is written to the same location (address 0) in the FIFO. The syn-
chronization algorithm issues a sync pulse and sync error signals to the read control block based on the alignment
option chosen. This sync pulse will coordinate the reading of the FIFOs.
The read control logic synchronizes the reading of the FIFO for the streams that are to be aligned. The block begins
reading when the FIFO sync sub block signals that all of the applicable A1s with the appropriate margin have been
written to the FIFO. All of the read blocks to be synchronized begin reading at the same time and same location in
the memory (address 0). The block also takes the difference between the write and read address to indicate the rel-
ative skews between the links. If this difference exceeds a certain limit (programmable), then an alarm (alignment
overow) is provided to the register interface.
Multi-channel Alignment in SONET Mode – ORSO42G5
The alignment FIFO allows the transfer of all data to a common clock. The FIFO sync block allows the system to be
congured to allow the frame alignment of multiple slightly varying data streams. This optional alignment ensures
that matching SERDES streams will arrive at the FPGA end in perfect data sync. It is important to note that for all
aligned channels in a group, the SERDES transmitters on the other side of the high-speed link must all be transmit-
ting data at exactly the same frequency (0 ppm difference), i.e., using a common clock source.
The ORSO42G5 has a total of four channels (two per SERDES block). The incoming data of these channels can
be synchronized in several ways, or they can be independent of one other. Two channels within a SERDES can be
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ORT82G5-1FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| ORT82G5-2FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| VI-J4H-IW-F4 | CONVERTER MOD DC/DC 52V 100W |
| VI-J4H-IW-F3 | CONVERTER MOD DC/DC 52V 100W |
| ORT82G5-1FN680C | IC TRANCEIVERS FPSC 680FPBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORSO42G5-EV | 功能描述:可編程邏輯 IC 開(kāi)發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORSO82G5 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
| ORSO82G5-1BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1BM680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1F680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。