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| 型號(hào)： | ORSO42G5-3BMN484C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 24/153頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPGAM |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
12
Support for OC-48 and OC-192 (in block OC-48) formats.
SONET framing, scrambling and SONET Mode channel alignment.
Performance monitoring functions such as Bit Interleaved Parity (BIP-8) generation and checking and Out-Of-
Frame (OOF) and Remote Defect Indication (RDI-L) detection.
Cell Mode cell creation and extraction, idle cell insertion/deletion, destriping and striping functions.
Additionally, there are two independent memory blocks in the core. Each embedded RAM block has a capacity of
4K words by 36 bits.
The ORSO42G5 and ORSO82G5 embedded cores contain, respectively, four-channel and eight-channel clock and
data recovery macrocells and logical blocks performing functions such as SONET framing, scrambling/descram-
bling and cell processing. The channels each operate from 0.6 to 2.7 Gbps with per channel CDR functionality. The
CDR interface enables high-speed asynchronous serial data transfer between system devices. Devices can be on
the same PC-board, on separate boards connected across a backplane, or connected by cables. Figure 2 shows a
top level block diagram of the backplane driver logic in the embedded core (embedded RAM not shown).
Figure 2. Top Level Block Diagram ORSO42G5 and ORSO82G5 Embedded Cores
ORSO42G5 and ORSO82G5 Main Operating Modes - Overview
The ORSO42G5 and ORSO82G5 support four and eight 0.6 to 2.7 Gbps serial data channels respectively, which
can operate independently or can be combined together (aligned) to achieve higher bit rates. The mode of opera-
tion of the core is dened by a set of control registers, which can be written through the system bus interface. The
status of the core is stored in a set of status registers, which can be read through the system bus interface.
The serial data channels support OC-48 rates on each channel. The standard OC-48 rate, 2.488 Gbits, is used as
the nominal data rate for the technical discussions that follow. OC-192 is also supported but is transmitted and
received in block OC-48 links. The scrambled data stream conforms to the GR-255 specied polynomial sequence
of 1+x
6+x7.
There are three main operating modes in the ORSO42G5 and ORSO82G5 as described below:
SERDES only (bypass) mode
SONET mode
Cell mode
– Two-link sub-mode
– Eight-link sub-mode (ORSO82G5 only)
Transmit (TX) Path
Receive (RX) Path
Cell
Processing
Configurable
as
four
or
eight
data
channels
organized
in
two
blocks
User
Configurable
I/O
Psuedo-
SONET
Processing
ORCA 4E04
FPGA Logic
MUX/DEMUX
and
SERDES
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ORT82G5-1FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| ORT82G5-2FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| VI-J4H-IW-F4 | CONVERTER MOD DC/DC 52V 100W |
| VI-J4H-IW-F3 | CONVERTER MOD DC/DC 52V 100W |
| ORT82G5-1FN680C | IC TRANCEIVERS FPSC 680FPBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORSO42G5-EV | 功能描述:可編程邏輯 IC 開(kāi)發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類(lèi)型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類(lèi)型: 工作電源電壓: |
| ORSO82G5 | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
| ORSO82G5-1BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1BM680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1F680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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