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| 型號(hào)： | ORSO42G5-3BMN484C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 106/153頁(yè) |
| 文件大小： | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPGAM |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
56
Cell Mode Receive Path
The receive logic blocks unique to the cell mode are shown in Figure 43 and are described in the next sections.
Prior to reaching this logic the received data has been demultiplexed, frame aligned and descrambled by the SER-
DES and SONET logic and is formatted on a per channel basis as 32-bit words with an accompanying clock. The
clock is a 77.76 MHz clock provided by the DEMUX block performing a divide-by-4 operation on RWCKxx.
The Data Extractor and receive FIFO (RXFIFO) process the data on a per channel basis. The receive FIFO also
performs a clock domain transfer to the 156 MHz domain of the Input Port Controller (IPC2/8) blocks. The IPC2/8
blocks perform the two-link or eight-link (ORSO82G5 only) alignment functions. In two-link alignment mode, the
received data are passed to the FPGA logic as 40-bit words at the 156 MHz rate. In eight-link alignment mode, the
received data are passed to the FPGA logic as a single 160-bit word, again at the 156 MHz rate. Additional mode-
dependent status information is also provided across the Core/FPGA interface.
Figure 43. Receive Path Logic Unique to Cell Mode
Cell Extractor
This block is used only in cell mode and does the following:
Extracts User cells from the SPE
Performs BIP calculation/checks to verify cell integrity
Link Header Sequence Interrogation
Processing options include:
Cell handling for invalid sequence (drop or pass to FPGA)
S/W congurable ‘link removal’ due to excessive sequence errors
Data from the cell extractor block(s) is sent to the receive FIFO which aligns the data to the system clock domain
and provides for deskew between the links.
Cell Extraction and BIP Calculation/Checking
The data from the descrambler are passed into the data extractor which strips the cell data from the payload of a
SONET frame. The block extracts the BIP value from the data stream and also perform an internal cell BIP calcula-
tion. If the BIP value is not correct, an error ag bit will set in the status registers. The block also determines when
the next Link Header is coming in the frame and what the cell sequence number contained within it should be. If the
value of the cell sequence counter is not equal to the expected value, an error ag bit will set in the status registers
and an error signal will be sent across the core/FPGA interface.
RX FIFO Data from Other Channel
Cell
Extractor
RX
FIFO
Write
IPC2
Control
FIFO
Read
Control
or
IPC8
Block
in Two-Link Alignment Group
RX FIFO Data from Other
Channels in Eight-Link
Alignment Group
IPC2_[A:B][1:2]
or IPC8
SYSCLK156[A:B][1:2]
or SYSCLK156 8
6
32
77.76 MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ORT82G5-1FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| ORT82G5-2FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| VI-J4H-IW-F4 | CONVERTER MOD DC/DC 52V 100W |
| VI-J4H-IW-F3 | CONVERTER MOD DC/DC 52V 100W |
| ORT82G5-1FN680C | IC TRANCEIVERS FPSC 680FPBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORSO42G5-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORSO82G5 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
| ORSO82G5-1BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1BM680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1F680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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