參數(shù)資料
型號： ORSO42G5-3BMN484C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 96/153頁
文件大小： 0K
描述： IC TRANCEIVERS FPSC 680FPGAM
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
47
ORSO42G5 Conguration
At startup, the legacy SERDES channel logic must be powered down and removed from any multi-channel align-
ment groups:
Setting bit 1 to one in registers at locations 30002, 30012, 30102 and 30112 powers down the legacy logic. (Note
that the reset value for these bits is 0.)
Setting bit 1 to zero (reset condition) in the register at locations 30802, 30812, 30902 and 30912 removes the
legacy logic from any alignment group.
Register settings for SONET multi-channel alignment are shown in Table 7.
Table 7. Multichannel Alignment Modes – ORSO42G5
To align two channels in SERDES A:
FMPU_SYNMODE_AC = 01 (Register Location 30822)
FMPU_SYNMODE_AD = 01 (Register Location 30832)
To align two channels in SERDES B:
FMPU_SYNMODE_BC = 01 (Register Location 30922)
FMPU_SYNMODE_BD = 01 (Register Location 30932)
To align all four channels:
FMPU_SYNMODE_AC = 11 (Register Location 30822)
FMPU_SYNMODE_AD = 11 (Register Location 30832)
FMPU_SYNMODE_BC = 11 (Register Location 30922)
FMPU_SYNMODE_BD = 11 (Register Location 30932)
To enable/disable multi-channel alignment of individual channels within a multi-channel alignment group:
FMPU_STR_EN_xx = 1 enabled
FMPU_STR_EN_xx = 0 disabled
where xx = [AC,AD,BC,BD]
To resynchronize a multichannel alignment group set the following bits to one, and then set to zero:
FMPU_RESYNC4 for four channels, AC, AD, BC and BD. (Register Location 30A04, bit 7)
FMPU_RESYNCA2 for dual channels, AC and AD. (Register Location 30A04, bit 2)
FMPU_RESYNCB2 for dual channels, BC and BD. (Register Location 30A04, bit 5)
To resynchronize an independent channel (resetting the write and the read pointer of the FIFO) set the following
bits to one, and then set to zero.
FMPU_RESYNC1_xx (Register Locations 30824, 20834, 30924 and 30934, bit 7) where xx is one of AC, AD, BC
or BD.
Register Bits
FMPU_SYNMODE_xx[2:3]
Mode
00
No multichannel alignment
01
Twin channel alignment
11
Four channel alignment
Note: xx = [AC,AD,BC,BD]
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORSO42G5-EV 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
ORSO82G5 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO82G5-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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