參數(shù)資料
型號(hào)： ORSO42G5-3BMN484C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 133/153頁
文件大?。?/td> 0K
描述： IC TRANCEIVERS FPSC 680FPGAM
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
80
Table 24. SERDES Per Channel Conguration Registers (Read/Write) – ORSO42G5
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
SERDES Per Channel Transmit and Receive Channel Conguration Registers (Read/Write) xx = [AC, AD, BC, BD]
30024 - AC
30034 - AD
30124 - BC
30134 - BD
[0]
RSVD
40
Reserved
—
[1]
MASK_xx
Transmit and Receive Alarm Mask Bit, Channel
xx. When MASK_xx = 1, the transmit and
receive alarms of a channel are prevented from
generating an alarm (i.e., they are masked or
disabled). The MASK_xx bit overrides the indi-
vidual alarm mask bits in the Alarm Mask Reg-
isters.
MASK_xx = 1 on device reset.
Both
[2]
SWRST_xx
Transmit and Receive Software Reset Bit,
Channel xx. When SWRST_xx = 1, this bit pro-
vides the same function as the hardware reset,
except that all conguration register settings are
unaltered. This is not a self-clearing bit. Once
set, this bit must be manually set and cleared.
SWRST = 0 on device reset.
Both
[3:6]
RSVD
Reserved
—
[7]
TESTEN_xx
Transmit and receive Test Enable Bit, Channel
xx. When TESTEN_xx = 1, the transmit and
receive sections of channel xx are place in test
mode. The TESTMODE_xx bits (30006, 30106,
etc.) must be set to specify the desired test. The
GTESTEN_[A:B] bits override the individual
TESTEN_xx settings.
Both
30026-AC
30036-AD
30126-BC
30136-BD
[0]
TESTMODE_xx
00
SERDES Test Mode Select, channel xx.
TESTMODE_xx = 0 selects Near End Loopback
(CML TX to CML RX internally)
TESTMODE_xx = 1 selects Far End Loopback
(CML RX to CML TX internally)
Factory
Test
[1:7]
RSVD
Reserved, Set to zero (default).
—
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