- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11733 > ORSO42G5-3BMN484C (Lattice Semiconductor Corporation)IC TRANCEIVERS FPSC 680FPGAM PDF資料下載
參數(shù)資料
| 型號(hào)： | ORSO42G5-3BMN484C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 143/153頁(yè) |
| 文件大小： | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPGAM |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | * |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)當(dāng)前第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
9
Routing
The abundant routing resources of the Series 4 architecture are organized to route signals individually or as buses
with related control signals. Both local and global signals utilize high-speed buffered and nonbuffered routes. One
PLC segmented (x1), six PLC segmented (x6), and bused half chip (xHL) routes are patterned together to provide
high connectivity with fast software routing times and high-speed system performance.
Eight fully distributed primary clocks are routed on a low-skew, high-speed distribution network and may be
sourced from dedicated I/O pads, PLLs, PLC logic or the Embedded Core. Secondary and edge-clock routing is
available for fast regional clock or control signal routing for both internal regions and on device edges. Secondary
clock routing can also be sourced from any I/O pin, PLLs, PLC logic or the Embedded Core.
The improved routing resources offer great exibility in moving signals to and from the logic core. This exibility
translates into an improved capability to route designs at the required speeds when the I/O signals have been
locked to specic pins.
System Level Features
The Series 4 also provides system-level functionality by means of its MicroProcessor Interface, Embedded System
Bus, block-port Embedded Block RAMs, universal Programmable Phase-Locked Loops, and the addition of highly
tuned networking specic Phase-Locked Loops. These functional blocks allow for easy glueless system interfacing
and the capability to adjust to varying conditions in today’s high-speed networking systems.
MicroProcessor Interface
The MPI provides a glueless interface between the FPGA and PowerPC microprocessors. Programmable in 8-,
16-, and 32-bit interfaces with optional parity to the Motorola
PowerPC 860 bus, it can be used for conguration
and readback, as well as for FPGA control and monitoring of FPGA status. All MPI transactions utilize the Series 4
Embedded System Bus at 66 MHz performance.
The MicroProcessor Interface (MPI) provides a system-level interface, using the system bus, to the FPGA user-
dened logic following conguration, including access to the Embedded Block RAM and general logic. The MPI
supports burst data read and write transfers, allowing short, uneven transmission of data through the interface by
including data FIFOs. Transfer accesses can be single beat (1 x 4 bytes or less), 4-beat (4 x 4 bytes), 8-beat (8 x 2
bytes), or 16-beat (16 x 1 bytes).
System Bus
An on-chip, multimaster, 32-bit system bus with 4-bit parity facilitates communication among the MPI, conguration
logic, FPGA control, and status registers, Embedded Block RAMs, as well as user logic. The Embedded System
Bus offers arbiter, decoder, master, and slave elements. Master and slave elements are also available for the user-
logic and a slave interface is used for control and status of the embedded backplane transceiver portion of the
ORSO42G5 and ORSO82G5.
The system bus control registers can provide control to the FPGA such as signaling for reprogramming, reset func-
tions, and PLL programming. Status registers monitor INIT, DONE, and system bus errors. An interrupt controller is
integrated to provide up to eight possible interrupt resources. Bus clock generation can be sourced from the Micro-
Processor Interface clock, conguration clock (for slave conguration modes), internal oscillator, user clock from
routing, or from the port clock (for JTAG conguration modes).
Phase-Locked Loops
Up to eight PLLs are provided on each Series 4 device, with four user PLLs generally provided for FPSCs, includ-
ing the ORSO42G5 and ORSO82G5. In the FPSCs, these PLLs can only be driven by the FPGA resources. Pro-
grammable PLLs can be used to manipulate the frequency, phase, and duty cycle of a clock signal. Each PPLL is
capable of manipulating and conditioning clock outputs from 15 MHz to 420 MHz. Frequencies can be adjusted
from 1/8x to 8x, the input clock frequency. Each programmable PLL provides two outputs that have different multi-
plication factors but can have the same phase relationships. Duty cycles and phase delays can be adjusted in
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ORT82G5-1FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| ORT82G5-2FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| VI-J4H-IW-F4 | CONVERTER MOD DC/DC 52V 100W |
| VI-J4H-IW-F3 | CONVERTER MOD DC/DC 52V 100W |
| ORT82G5-1FN680C | IC TRANCEIVERS FPSC 680FPBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORSO42G5-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORSO82G5 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
| ORSO82G5-1BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1BM680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1F680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。