參數資料
型號: P60ARM-B
廠商: Zarlink Semiconductor Inc.
英文描述: Low power, general purpose 32-bit RISC microprocessor
中文描述: 低功耗,通用32位RISC微處理器
文件頁數: 112/120頁
文件大?。?/td> 1275K
代理商: P60ARM-B
108
P60ARM-B
Figure 42: Data Bus Control
Note:
The cycle shown is a data write cycle. Here,
bus.
DBE
has been used to modify the behaviour of the data
Figure 43: Configuration Pin Timing
Figure 44: Coprocessor Timing
Note:
Normally,
ARM has been busy-waiting, waiting for a coprocessor to complete the instruction. If
change during phase 1, the timing of
nMREQ
should be able to generate
CPA
and
CPB
during the previous phase 2, and so the timing of
and
SEQ
will always be Tmsd.
nMREQ
and
SEQ
become valid Tmsd after the falling edge of
MCLK
. In this cycle the
CPA
and
CPB
and
SEQ
will depend on Tcpms. Most systems
nMREQ
MCLK
D[31:0]
DBE
T
de
T
dout
T
doh
T
dz
T
dbz
T
dbe
MCLK
LATEABT,
BIGEND,
DATA32,
PROG32
T
cth
T
cts
MCLK
nCPI
CPA, CPB
nMREQ,
SEQ
T
cpi
T
cpih
T
cps
T
cph
T
cpms
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相關代理商/技術參數
參數描述
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