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參數(shù)資料
| 型號： | P60ARM-B |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Low power, general purpose 32-bit RISC microprocessor |
| 中文描述： | 低功耗，通用32位RISC微處理器 |
| 文件頁數(shù)： | 72/120頁 |
| 文件大小： | 1275K |
| 代理商： | P60ARM-B |
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P60ARM-B
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Figure 31: Decoding Byte Accesses to Memory
5.3 Address timing
Normally the processor address changes during phase 2 to the value which the memory system should use
during the following cycle. This gives maximum time for driving the address to large memory arrays, and
for address translation where required. Dynamic memories usually latch the address on chip, and if the
latch is timed correctly they will work even though the address changes before the access has completed.
Static RAMs and ROMs will not work under such circumstances, as they require the address to be stable
until after the access has completed. Therefore, for use with such devices, the address transition must be
delayed until after the end of phase 2. An on-chip address latch, controlled by
timing to be modified in this way. In a system with a mixture of static and dynamic memories (which for
these purposes means a mixture of devices with and without address latches), the use of
dynamically from one cycle to the next, at the discretion of the memory system.
ALE
, allows the address
ALE
may change
5.4 Memory management
The ARM60 address bus may be processed by an address translation unit before being presented to the
memory, and ARM60 is capable of running a virtual memory system. The abort input to the processor may
be used by the memory manager to inform ARM60 of page faults. Various other signals enable different
page protection levels to be supported:
(1)
nRW
can be used by the memory manager to protect pages from being written to.
(2)
nTRANS
protect system pages from the user, or to support completely separate mappings for the system and
the user.
indicates whether the processor is in user or a privileged mode, and may be used to
A[0]
A[1]
nBW
MCLK
CAS
NCAS0
NCAS1
NCAS2
NCAS3
G
D
Q
Quad
Latch
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