- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367700 > P60ARM-B (Zarlink Semiconductor Inc.) Low power, general purpose 32-bit RISC microprocessor PDF資料下載
參數(shù)資料
| 型號： | P60ARM-B |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Low power, general purpose 32-bit RISC microprocessor |
| 中文描述： | 低功耗，通用32位RISC微處理器 |
| 文件頁數(shù)： | 45/120頁 |
| 文件大小： | 1275K |
| 代理商： | P60ARM-B |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁當(dāng)前第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁
Instruction Set - LDM, STM
41
4.8 Block data transfer (LDM, STM)
The instruction is only executed if the condition is true. The various conditions are defined at the beginning
of this chapter. The instruction encoding is shown in
Figure 18: Block Data Transfer Instructions
.
Block data transfer instructions are used to load (LDM) or store (STM) any subset of the currently visible
registers. They support all possible stacking modes, maintaining full or empty stacks which can grow up or
down memory, and are very efficient instructions for saving or restoring context, or for moving large blocks
of data around main memory.
4.8.1 The register list
The instruction can cause the transfer of any registers in the current bank (and non-user mode programs
can also transfer to and from the user bank, see below). The register list is a 16 bit field in the instruction,
with each bit corresponding to a register. A 1 in bit 0 of the register field will cause R0 to be transferred, a
0 will cause it not to be transferred; similarly bit 1 controls the transfer of R1, and so on.
Any subset of the registers, or all the registers, may be specified. The only restriction is that the register list
should not be empty.
Whenever R15 is stored to memory the stored value is the address of the STM instruction plus 12.
Figure 18: Block Data Transfer Instructions
4.8.2 Addressing modes
The transfer addresses are determined by the contents of the base register (Rn), the pre/post bit (P) and the
up/down bit (U). The registers are transferred in the order lowest to highest, so R15 (if in the list) will
always be transferred last. The lowest register also gets transferred to/from the lowest memory address. By
way of illustration, consider the transfer of R1, R5 and R7 in the case where Rn=0x1000 and write back of
Cond
Rn
0
15
16
19
20
21
24
25
27
28
31
P U
W L
22
23
100
S
Register list
Base register
Load/Store bit
1 = Load from memory
Write-back bit
1 = write address into base
PSR & force user bit
1 = load PSR or force user mode
Up/Down bit
1 = up; add offset to base
Pre/Post indexing bit
1 = pre; add offset before transfer
Condition field
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P60A | 60W DC-DC Converter P60A-Series |
| P60A12D05P | 60W DC-DC Converter P60A-Series |
| P60A12D12P | 60W DC-DC Converter P60A-Series |
| P60A12D15P | 60W DC-DC Converter P60A-Series |
| P60A12D512P | 60W DC-DC Converter P60A-Series |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P60ARM-GP1N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Low power, general purpose 32-bit RISC microprocessor |
| P60ARM-IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Low power, general purpose 32-bit RISC microprocessor |
| P-60AS/A18 | 功能描述:BATTERY NICAD 2/3A 600MAH W/TAB RoHS:否 類別:電池產(chǎn)品 >> 電池，充電式（蓄電池） 系列:- MSDS 材料安全數(shù)據(jù)表:Nickel Metal Hydride Battery MSDS 標(biāo)準(zhǔn)包裝:1,000 系列:TWICELL 電池化學(xué):鎳金屬氫化物 電池大小:AAA 電壓 - 額定:1.2V 容量:930mAh 尺寸/尺寸:- 端接類型:焊片 放電速率:186mA 標(biāo)準(zhǔn)充電電流:100mA 標(biāo)準(zhǔn)充電時(shí)間:16小時(shí) 重量:0.029 磅（13.15g） 裝運(yùn)信息:- 其它名稱:SY153T |
| P60AS302 | 制造商:APEM 功能描述: |
| P60AS632-8C | 制造商:NYLOK 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。