參數(shù)資料
型號(hào): PC87393F-VJG
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 外設(shè)及接口
英文描述: 100-Pin LPC SuperI/O Devices for Portable Applications
中文描述: MULTIFUNCTION PERIPHERAL, PQFP100
封裝: TQFP-100
文件頁(yè)數(shù): 124/148頁(yè)
文件大?。?/td> 1733K
代理商: PC87393F-VJG
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3.0 General-Purpose Input/Output (GPIO) Port (Continued)
77
www.national.com
3.4.2
GPIO Pin Event Routing (GPEVR) Register
This is a group of eight identical configuration registers, each of which is associated with one GPIO pin. The entire set is
mapped to the PnP configuration space. The mapping scheme is based on the GPSEL register that functions as an index
register, and the specific GPER register that reflects the routing configuration of the currently selected pin. For details on the
GPSEL register, refer to the
This set of registers is applicable only for the enhanced GPIO port with event detection support. In the basic port this register
set is reserved, returns 0 on read and has no effect on port functionality.
Location:
Device specific
Type:
R/W
3.4.3
GPIO Port Runtime Register Map
Bit
76543210
Name
Reserved
GPIO Event
to SMI
Enable
GPIO Event
to IRQ
Enable
Reset
00000001
Bit
Description
7-2
Reserved
1
GPIO Event to SMI Enable. This bit is used to enable/disable the routing of the corresponding detected GPIO
event to SMI.
0: Disabled (default)
1: Enabled
0
GPIO Event to IRQ Enable. This bit is used to enable/disable the routing of the corresponding detected GPIO
event to IRQ.
0: Disabled
1: Enabled (default)
Offset
Mnemonic
Register Name
Type
Section
Device specic 1
1. The location of this register is dened in the
ter in Section 2.15.1.
GPDO
GPIO Data Out
R/W
Device specic 1
GPDI
GPIO Data In
RO
Device specic 1
GPEVEN
GPIO Event Enable
R/W
Device specic 1
GPEVST
GPIO Event Status
R/W1C
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