參數(shù)資料
型號： PC87393F-VJG
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 外設(shè)及接口
英文描述： 100-Pin LPC SuperI/O Devices for Portable Applications
中文描述： MULTIFUNCTION PERIPHERAL, PQFP100
封裝： TQFP-100
文件頁數(shù)： 135/148頁
文件大?。?/td> 1733K
代理商： PC87393F-VJG
5.0 Game Port (GMP) (Continued)
87
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5.2.5
Operation Control
When the Game Port is operated in Legacy mode, it can only be operated by polling (see Section 5.2.4,
When the Game Port is operated in Enhanced mode, both kinds of status reading operations (position and button) can be
performed using polling or interrupt controlled operation.
If polling controlled operation is preferred, the software should poll either the GMPLST register for the direct status of the
buttons as in Legacy mode, or the GMPXST register which provides indications regarding button events detected by hard-
ware. The GMPXST register should also be polled for the status of the position counters. When the status is ready, the
counter values can be read. These values reflect the positions indicated by the game device.
If interrupt controlled operation is preferred, the software should first define the events on which an interrupt request is to be
issued. This is done by writing the required values to the GMPEPOL (see Section 5.3.14) and GMPIEN (see Section 5.3.5)
registers. The GMPEPOL register defines the events on which the buttons cause an interrupt request to be issued. These
events are all edge-triggered. The GMPIEN register determines what events are physically routed to the interrupt request
assigned to the Game Port. An independent interrupt enable bit is implemented in the GMPIEN register for each one of the
four buttons and two position counters of the two supported game devices.
5.3
GAME PORT REGISTERS
The following abbreviations are used to indicate the Register Type:
q
R/W = Read/Write
q
R = Read from a specic address returns the value of a specic register. Write to the same address is to a different
register.
q
W=Write
q
RO = Read Only
q
R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
5.3.1
Game Port Register Map
The following table lists the Game Port registers. for the Game Port register bitmap, see Section 5.4.
Offset
Mnemonic
Register Name
Type
Section
00h
GMPCTL Game Port Control
R/W
01h
GMPLST
Game Port Legacy Status
RO
02h
GMPXST Game Port Extended Status
R/W1C
03h
GMPIEN
Game Port Interrupt Enable
R/W
04h
GMPAXL
Game Device A X Position Low Byte
RO
05h
GMPAXH Game Device A X Position High Byte
RO
06h
GMPAYL
Game Device A Y Position Low Byte
RO
07h
GMPAYH
Game Device A Y Position High Byte
RO
08h
GMPBXL Game Device B X Position Low Byte
RO
09h
GMPBXH Game Device B X Position High Byte
RO
0Ah
GMPBYL Game Device B Y Position Low Byte
RO
0Bh
GMPBYH Game Device B Y Position High Byte
RO
0Ch
GMPEPOL Game Port Event Polarity
R/W
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