參數(shù)資料
型號(hào)： PC87393F-VJG
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： 外設(shè)及接口
英文描述： 100-Pin LPC SuperI/O Devices for Portable Applications
中文描述： MULTIFUNCTION PERIPHERAL, PQFP100
封裝： TQFP-100
文件頁(yè)數(shù)： 91/148頁(yè)
文件大?。?/td> 1733K
代理商： PC87393F-VJG
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2.0 Device Architecture and Configuration (Continued)
47
www.national.com
2.11 FLOPPY DISK CONTROLLER (FDC) CONFIGURATION
2.11.1
General Description
The generic FDC is a standard FDC with a digital data separator, and is DP8473 and N82077 software compatible. The PC8739x
FDC supports 14 of the 17 standard FDC signals described in the generic Floppy Disk Controller (FDC) chapter, including:
q
FM and MFM modes are supported. To select either mode, set bit 6 of the rst command byte when writing to/read-
ing from a diskette, where:
0 = FM mode
1 = MFM mode
q
A logic 1 is returned for all oating (TRI-STATE) FDC register bits upon LPC I/O read cycles.
Exceptions to standard FDC support include:
q
Automatic media sense is supported by MSEN1-0 pins only on FDC signals routed to the PPM functional block (on
the Parallel Port)
q
DRATE1 is supported only on FDC signals routed to the PPM functional block (on the Parallel Port).
Table 16 lists the FDC functional block registers.
Table 16. FDC Registers
2.11.2
Logical Device 0 (FDC) Configuration
Table 17 lists the configuration registers which affect the FDC. Only the last two registers (F0h and F1h) are described here.
See Sections 2.2.3 and 2.2.4 for descriptions of the others.
Table 17. FDC Conguration Registers
Offset1
1. From the 8-byte aligned FDC base address.
Mnemonic
Register Name
Type
00h
SRA
Status A
RO
01h
SRB
Status B
RO
02h
DOR
Digital Output
R/W
03h
TDR
Tape Drive
R/W
04h
MSR
Main Status
R
DSR
Data Rate Select
W
05h
FIFO
Data (FIFO)
R/W
06h
N/A
X
07h
DIR
Digital Input
R
CCR
Conguration Control
W
Index
Conguration Register or Action
Type
Reset
30h
Activate. See also bit 0 of the SIOCF1 register and bit 0 of the SIOCF6 register. R/W
00h
60h
Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b.
R/W
03h
61h
Base Address LSB register. Bits 2 and 0 (for A2 and A0) are read only, 00b.
R/W
F2h
70h
Interrupt Number and Wake-Up on IRQ Enable register
R/W
06h
71h
Interrupt Type. Bit 1 is read/write; other bits are read only.
R/W
03h
74h
DMA Channel Select
R/W
02h
75h
Report no second DMA assignment
RO
04h
F0h
FDC Conguration register
R/W
24h
F1h
Drive ID register
R/W
00h
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PC87393VJG 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:IC, SUPER I/O DEVICE, TQFP-100, Logic Device Type:Buffer, Supply Voltage Min:3V,
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