參數(shù)資料
型號： PCI1620PDV
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 133/164頁
文件大小： 720K
代理商： PCI1620PDV
6
–
1
6 CardBus Socket Registers (Functions 0 and 1)
The
1997 PC Card Standard
requires a CardBus socket controller to provide five 32-bit registers that report and
control socket-specific functions. The PCI1620 provides the CardBus socket/ExCA base address register (offset 10h,
see Section 4.12) to locate these CardBus socket registers in PCI memory address space. Each function has a
separate base address register for accessing the CardBus socket registers (see Figure 6
–
1). Table 6
–
1 gives the
location of the socket registers in relation to the CardBus socket/ExCA base address.
In addition to the five required registers, the PCI1620 implements a register at offset 20h that provides power
management control for the socket.
CardBus Socket/ExCA Base Address
16-Bit Legacy-Mode Base Address
10h
44h
NOTE: The CardBus socket/ExCA base address mode register is separate for functions 0 and 1.
PCI1620 Configuration Registers
CardBus
Socket A
Registers
Host
Memory Space
00h
ExCA
Registers
Card A
20h
800h
844h
Offset
CardBus
Socket B
Registers
Host
Memory Space
00h
ExCA
Registers
Card B
20h
800h
844h
Offset
Offset
Figure 6
–
1. Accessing CardBus Socket Registers Through PCI Memory
Table 6
–
1. CardBus Socket Registers
REGISTER NAME
OFFSET
Socket event
Socket mask
00h
04h
Socket present state
08h
Socket force event
Socket control
0Ch
10h
Reserved
14h
–
1Ch
Socket power management
20h
One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then these bits are cleared by the assertion of PRST or GRST.
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