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參數(shù)資料
| 型號(hào)： | PCI1620PDV |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 48/164頁(yè) |
| 文件大?。?/td> | 720K |
| 代理商： | PCI1620PDV |
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3
–
6
Table 3
–
1. Serial EEPROM Map (Continued)
EEPROM
OFFSET
PCI/ExCA
OFFSET
REGISTER BITS LOADED FROM EEPROM
21h
PCI 64h
Reserved
–
load all 0s
22h
PCI 65h
Reserved
–
load all 0s
23h
PCI 66h
Reserved
–
load all 0s
24h
PCI 67h
Reserved
–
load all 0s
25h
PCI 68h
Reserved
–
load all 0s
26h
PCI 6Ch
Subsystem vendor ID (firmware loader function) byte 0
27h
PCI 6Dh
Subsystem vendor ID (firmware loader function) byte 1
28h
PCI 6Eh
Subsystem ID (firmware loader function) byte 0
29h
PCI 6Fh
Subsystem ID (firmware loader function) byte 1
3.4.4
Loading the Subsystem Identification (EEPROM Interface)
The subsystem vendor ID register and subsystem ID register make up a doubleword of PCI configuration space
located at offset 40h for functions 0 and 1. This doubleword register, used for system and option card (mobile dock)
identification purposes, is required by some operating systems. Implementation of this unique identifier register is
a
PC Card Standard
requirement.
The PCI1620 offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism
relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers
is read-only, but the access mode can be made read/write by clearing the SUBSYSRW bit (bit 5) of the system control
register (PCI offset 80h, see Section 4.28). Once this bit is cleared (0), the BIOS can write a subsystem identification
value into the registers at offset 40h. The BIOS must set the SUBSYSRW bit such that the subsystem vendor ID
register and subsystem ID register are limited to read-only access.
In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register
can be loaded with a unique identifier through a serial EEPROM interface. The PCI1620 loads the doubleword of data
from the serial EEPROM after a reset of the primary bus. (Note that the SUSPEND input gates PRST and GRST from
the entire PCI1620 core, including the serial EEPROM state machine. See Section 3.6.6,
Suspend Mode
, for details
on using SUSPEND.) The PCI1620 provides a two-line serial bus interface to the serial EEPROM.
The system designer must implement a pulldown resistor on the PCI1620 LATCH terminal to indicate the serial
EEPROM mode. Only when this pulldown resistor is present does the PCI1620 attempt to load data through the serial
EEPROM interface. Figure 3
–
3 illustrates a typical PCI1620 application using the serial EEPROM interface.
3.5
PC Card Applications Overview
This section describes the PC Card interfaces of the PCI1620. A discussion on PC Card recognition details the card
interrogation procedure. This section discusses the card powering procedure, including the protocol of the P
2
C power
switch interface, and ZV routing. It also describes standard PC Card register models and briefly discusses the PC
Card software protocol layers.
3.5.1
Card Detection in an UltraMedia System
The PCI1620 is capable of detecting all the UltraMedia devices defined by the PCMCIA
Proposal 0262
–
Smart Media
cards, MultiMedia Cards, Multimedia Card
–
Secure Digital, Memory Stick devices, and Smart Card devices. The
detection of these devices is made possible through circuitry included in the PCI1620 and the UltraMedia Adapters
used to interface these devices with the PC Card/CardBus sockets. No additional hardware requirements are placed
on the system designer in order to support these devices.
The
PC Card Standard
addresses the card detection and recognition process through an interrogation procedure that
the socket must initiate upon card insertion into a cold, unpowered socket. Through this interrogation, card voltage
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