參數(shù)資料
型號： PCI1620PDV
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 58/164頁
文件大?。?/td> 720K
代理商： PCI1620PDV
3
–
16
3.5.10.2
Firmware Loader Control Register
This register contains various control and status bits for the firmware loader. Bit descriptions are given in Table 3
–
10.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Firmware loader control
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Firmware loader control
Type
R
R
R
R
R
R
R
R
R
R
R
R
W
W
R
RU
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Firmware loader control
04h
Read-only, Write-only, Read/Update
0000 0000h
Table 3
–
10. Firmware Loader Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
31
–
4
RSVD
R
Reserved. These bits are read-only and return 0s when read.
3
ADDR_RST
W
Address reset. When set, this bit indicates that the next data written to the data/address register will be a
doubleword that specifies the start address of the next block of internal RAM to be loaded. This bit is self-
cleared when the address is written to the data/address register.
2
DONE
W
RAM load done. Setting this bit to 1 indicates to the firmware loader function that the firmware loading is
complete for the RAM selected by the address written when ADDR_RST was set, and embedded control-
lers can begin accessing the RAM. This bit is self-clearing.
1
RSVD
R
Reserved. This bit is read-only and returns 0 when read.
0
ERR
RU
When set, this bit indicates that there was an error during the loading of the internal RAM. This field indicates
all loading errors. Software should check this bit after loading each RAM to insure that the data was loaded
successfully. This bit is cleared by a read of this register.
3.6
Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic
nature of PC Cards and the abundance of PC Card I/O applications require substantial interrupt support from the
PCI1620. The PCI1620 provides several interrupt signaling schemes to accommodate the needs of a variety of
platforms. The different mechanisms for dealing with interrupts in this device are based on various specifications and
industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the
CardBus socket register set provides interrupt control for the CardBus PC Card functions. The PCI1620 is, therefore,
backward compatible with existing interrupt control register definitions, and new registers have been defined where
required.
The PCI1620 detects PC Card interrupts and events at the PC Card interface and notifies the host controller using
one of several interrupt signaling protocols. To simplify the discussion of interrupts in the PCI1620, PC Card interrupts
are classified either as card status change (CSC) or as functional interrupts.
The method by which any type of PCI1620 interrupt is communicated to the host interrupt controller varies from
system to system. The PCI1620 offers system designers the choice of using parallel PCI interrupt signaling, parallel
ISA-type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. It is possible to use the
parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs, as detailed in the sections that
follow. All interrupt signaling is provided through the seven multifunction terminals, MFUNC0
–
MFUNC6.
Programmable Interrupt Subsystem
3.6.1
PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are
indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by
16-bit I/O PC Cards and by CardBus PC Cards.
PC Card Functional and Card Status Change Interrupts
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