參數(shù)資料
型號： PCI1620PDV
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 57/164頁
文件大小： 720K
代理商： PCI1620PDV
3
–
15
3.5.10.1
Data/Address Register
When the ADDR_RST bit is set in the firmware loader control register (offset 04h, see Section 3.5.10.2) the next data
written to this register is a doubleword that specifies the start address of the next block of internal RAM to be loaded.
When the doubleword of address information is written to this field, the ADDR_RST bit is automatically cleared and
the following writes to this register represent the internal RAM data. Because the internal RAM in PCI1620 is 16 bits
wide, the internal RAM data written to this register is written one word at a time. The internal RAM address is
autoincremented after each word of internal RAM data is written to this location. It is appropriate to buffer requests
to the internal RAM and retry PCI writes to this register when the buffer is full. If the firmware loader is unable to update
the RAM, a PCI slave retry time-out occurs, data is lost, and the ERR bit in the control register is set. Reads from this
register return all 1s.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Data address
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Data address
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Register:
Offset:
Type:
Default:
Data address
00h
Read/Write
FFFF FFFFh
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