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參數(shù)資料
| 型號： | PCI1620PDV |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 63/164頁 |
| 文件大?。?/td> | 720K |
| 代理商： | PCI1620PDV |
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3
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21
3.7.2
Clock Run Protocol
The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCI1620. CLKRUN
signaling is provided through the MFUNC6 terminal. Since some chip sets do not implement CLKRUN, this is not
always available to the system designer, and alternate power-saving features are provided. For details on the
CLKRUN protocol see the
PCI Mobile Design Guide
.
The PCI1620 does not permit the central resource to stop the PCI clock under any of the following conditions:
Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.31) is set.
The 16-bit PC Card- resource manager is busy.
The PCI1620 CardBus master state machine is busy. A cycle may be in progress on CardBus.
The PCI1620 master is busy. There may be posted data from CardBus to PCI in the PCI1620.
Interrupts are pending.
The CardBus CCLK for either socket has not been stopped by the PCI1620 CCLKRUN manager.
The PCI1620 restarts the PCI clock using the CLKRUN protocol under any of the following conditions:
A 16-bit PC Card IREQ or a CardBus CINT has been asserted by either card.
A CardBus CBWAKE (CSTSCHG) or 16-bit PC Card STSCHG/RI event occurs in either socket.
A CardBus attempts to start the CCLK using CCLKRUN.
A CardBus card arbitrates for the CardBus bus using CREQ.
3.7.3
CardBus PC Card Power Management
The PCI1620 implements its own card power-management engine that can turn off the CCLK to a socket when there
is no activity to the CardBus PC Card. The PCI clock-run protocol is followed on the CardBus CCLKRUN interface
to control this clock management.
3.7.4
16-Bit PC Card Power Management
The COE bit (bit 7) of the ExCA power control register (ExCA offset 02h/42h/802h, see Section 5.3) and PWRDWN
bit (bit 0) of the ExCA global control register (ExCA offset 1Eh/5Eh/81Eh, see Section 5.20) bits are provided for 16-bit
PC Card power management. The COE bit places the card interface in a high-impedance state to save power. The
power savings when using this feature are minimal. The COE bit resets the PC Card when used, and the PWRDWN
bit does not. Furthermore, the PWRDWN bit is an automatic COE, that is, the PWRDWN performs the COE function
when there is no card activity.
NOTE:
The 16-bit PC Card must implement the proper pullup resistors for the COE and
PWRDWN modes.
3.7.5
Suspend Mode
The SUSPEND signal, provided for backward compatibility, gates the PRST (PCI reset) signal and the GRST (global
reset) signal from the PCI1620. Besides gating PRST and GRST, SUSPEND also gates PCLK inside the PCI1620
in order to minimize power consumption.
Gating PCLK does not create any issues with respect to the power switch interface in the PCI1620. This is because
the PCI1620 does not depend on the PCI clock to clock the power switch interface. There are two methods to clock
the power switch interface in the PCI1620:
Use an external clock to the PCI1620 CLOCK terminal
Use the internal oscillator
It should also be noted that asynchronous signals, such as card status change interrupts and RI_OUT, can be passed
to the host system without a PCI clock. However, if card status change interrupts are routed over the serial interrupt
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