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參數(shù)資料
| 型號： | PCI1620PDV |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 88/164頁 |
| 文件大?。?/td> | 720K |
| 代理商： | PCI1620PDV |
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4
–
20
Table 4
–
7
.
System Control Register Description (continued)
BIT
SIGNAL
TYPE
FUNCTION
5
SUBSYSRW
RW
Subsystem ID and subsystem vendor ID, ExCA ID and revision register read/write enable. This bit also
controls read/write for the function 2 subsystem ID register.
0 = Registers are read/write.
1 = Registers are read-only (default).
4
CB_DPAR
RW
CardBus data parity SERR signaling enable.
0 = CardBus data parity not signaled on PCI SERR signal (default)
1 = CardBus data parity signaled on PCI SERR signal
3
RSVD
RW
Reserved. To ensure proper device operation, do not alter the default value in this bit.
2
EXCAPOWER
R
ExCA power control bit.
0 = Enables 3.3 V (default)
1 = Enables 5 V
1
KEEPCLK
RW
Keep clock. When this bit is set, the PCI1620 follows the CLKRUN protocol to maintain the system
PCLK and the CCLK (CardBus clock). This bit is global to the PCI1620 functions.
0 = Allow system PCLK and CCLK to stop (default)
1 = Never allow system PCLK or CCLK clock to stop
Note that the functionality of this bit has changed relative to that of the PCI12XX family of TI CardBus
controllers. In these CardBus controllers, setting this bit only maintains the PCI clock, not the CCLK.
In the PCI1620, setting this bit maintains both the PCI clock and the CCLK.
0
RIMUX
RW
PME/RI_OUT select bit. When this bit is 1, the PME signal is routed to the PME/RI_OUT terminal (PDV
165, GHK E13). When this bit is 0 and bit 7 (RIENB) of the card control register is 1, the RI_OUT signal
is routed to the PME/RI_OUT terminal (PDV 165, GHK E13). If this bit is 0 and bit 7 (RIENB) of the card
control register is 0, then the output is placed in a high-impedance state. This terminal is encoded as:
0 = RI_OUT signal is routed to the PME/RI_OUT terminal (PDV 165, GHK E13) if bit 7 of the card
control register is 1. (default)
1 = PME signal is routed to the PME/RI_OUT terminal (PDV 165, GHK E13) of the PCI1620
controller.
NOTE: If this bit (bit 0) is 0 and bit 7 of the card control register (offset 91h, see Section 4.40) is 0, then
the output on the PME/RI_OUT terminal (PDV 165, GHK E13) is placed in a high-impedance state.
These bits are global in nature and should be accessed only through function 0.
4.32 MC_CD Debounce Register
This register provides debounce time in units of 2 ms for the MC_CD signal on UltraMedia cards. This register defaults
to19h, which gives a default debounce time of 50 ms. All bits in this register are reset by GRST only.
Bit
7
6
5
4
3
2
1
0
Name
MC_CD debounce
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
1
1
0
0
1
Register:
Offset:
Type:
Default:
MC_CD debounce
84h (Functions 0, 1)
Read/Write
19h
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