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參數(shù)資料
| 型號(hào)： | PCI1620PDV |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 71/164頁(yè) |
| 文件大?。?/td> | 720K |
| 代理商： | PCI1620PDV |
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4
–
3
4.4
Command Register
The PCI command register provides control over the PCI1620 interface to the PCI bus. All bit functions adhere to the
definitions in the
PCI Local Bus Specification
(see Table 4
–
2). None of the bit functions in this register are shared
among the PCI1620 PCI functions. Three command registers exist in the PCI1620, one for each function. Software
manipulates the PCI1620 functions as separate entities when enabling functionality through the command register.
The SERR_EN and PERR_EN enable bits in this register are internally wired OR between the three functions, and
these control bits appear to software to be separate for each function.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Command
Type
R
R
R
R
R
R
R
RW
R
RW
RW
R
R
RW
RW
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Command
04h
Read-only, Read/Write
0000h
Table 4
–
2. Command Register Description
BIT
SIGNAL
TYPE
FUNCTION
15
–
10
RSVD
R
Reserved. Bits 15
–
10 return 0s when read.
9
FBB_EN
R
Fast back-to-back enable. The PCI1620 does not generate fast back-to-back transactions; therefore, this
bit is read-only. This bit returns a 0 when read.
8
SERR_EN
RW
System error (SERR) enable. This bit controls the enable for the SERR driver on the PCI interface. SERR
can be asserted after detecting an address parity error on the PCI bus. Both this bit and bit 6 must be set
for the PCI1620 to report address parity errors.
0 = Disables the SERR output driver (default)
1 = Enables the SERR output driver
7
STEP_EN
R
Address/data stepping control. The PCI1620 does not support address/data stepping, and this bit is
hardwired to 0. Writes to this bit have no effect.
6
PERR_EN
RW
Parity error response enable. This bit controls the PCI1620 response to parity errors through the PERR
signal. Data parity errors are indicated by asserting PERR, while address parity errors are indicated by
asserting SERR.
0 = PCI1620 ignores detected parity errors (default).
1 = PCI1620 responds to detected parity errors.
5
VGA_EN
RW
VGA palette snoop. When set to 1, palette snooping is enabled (i.e., the PCI1620 does not respond to palette
register writes and snoops the data). When the bit is 0, the PCI1620 treats all palette accesses like all other
accesses.
4
MWI_EN
R
Memory write-and-invalidate enable. This bit controls whether a PCI initiator device can generate memory
write-and-invalidate commands. The PCI1620 controller does not support memory write-and-invalidate
commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. This bit returns
0 when read. Writes to this bit have no effect.
3
SPECIAL
R
Special cycles. This bit controls whether or not a PCI device ignores PCI special cycles. The PCI1620 does
not respond to special cycle operations; therefore, this bit is hardwired to 0. This bit returns 0 when read.
Writes to this bit have no effect.
2
MAST_EN
RW
Bus master control. This bit controls whether or not the PCI1620 can act as a PCI bus initiator (master). The
PCI1620 can take control of the PCI bus only when this bit is set.
0 = Disables the PCI1620 ability to generate PCI bus accesses (default)
1 = Enables the PCI1620 ability to generate PCI bus accesses
1
MEM_EN
RW
Memory space enable. This bit controls whether or not the PCI1620 can claim cycles in PCI memory space.
0 = Disables the PCI1620 response to memory space accesses (default)
1 = Enables the PCI1620 response to memory space accesses
0
IO_EN
RW
I/O space control. This bit controls whether or not the PCI1620 can claim cycles in PCI I/O space.
0 = Disables the PCI1620 from responding to I/O space accesses (default)
1 = Enables the PCI1620 to respond to I/O space accesses
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