參數(shù)資料
型號(hào)： PCI1620PDV
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 82/164頁(yè)
文件大?。?/td> 720K
代理商： PCI1620PDV
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4
–
14
4.25 Bridge Control Register
The bridge control register provides control over various PCI1620 bridging functions. Some bits in this register are
global in nature and should be accessed only through function 0. See Table 4
–
6 for a complete description of the
register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Bridge control
Type
R
R
R
R
R
RW
RW
RW
RW
RW
RW
R
RW
RW
RW
RW
Default
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Bridge control
3Eh (Function 0, 1)
Read-only, Read/Write
0340h
Table 4
–
6. Bridge Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
15
–
11
RSVD
R
These bits return 0s when read.
10
POSTEN
RW
Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables the
posting of write data on burst cycles. Operating with write posting disabled impairs performance on burst
cycles. Note that burst write data can be posted, but various write transactions may not. This bit is socket
dependent and is not shared between functions 0 and 1.
9
PREFETCH1
RW
Memory window 1 type. This bit specifies whether or not memory window 1 is prefetchable. This bit is
socket dependent. This bit is encoded as:
0 = Memory window 1 is nonprefetchable.
1 = Memory window 1 is prefetchable (default).
8
PREFETCH0
RW
Memory window 0 type. This bit specifies whether or not memory window 0 is prefetchable. This bit is
socket dependent. This bit is encoded as:
0 = Memory window 0 is nonprefetchable.
1 = Memory window 0 is prefetchable (default).
7
INTR
RW
PCI interrupt
–
IREQ routing enable. This bit is used to select whether PC Card functional interrupts are
routed to PCI interrupts or to the IRQ specified in the ExCA registers.
0 = Functional interrupts are routed to PCI interrupts (default).
1 = Functional interrupts are routed by ExCA registers.
6
CRST
RW
CardBus reset. When this bit is set, the CRST signal is asserted on the CardBus interface. The CRST
signal can also be asserted by passing a PRST assertion to CardBus.
0 = CRST is deasserted.
1 = CRST is asserted (default).
This bit is not cleared by the assertion of PRST. It is only cleared by the assertion of GRST.
5
MABTMODE
RW
Master abort mode. This bit controls how the PCI1620 responds to a master abort when the PCI1620 is
an initiator on the CardBus interface. This bit is common between each socket.
0 = Master aborts not reported (default).
1 = Signal target abort on PCI and signal SERR, if enabled.
4
RSVD
R
This bit returns 0 when read.
3
VGAEN
RW
VGA enable. This bit affects how the PCI1620 responds to VGA addresses. When this bit is set, accesses
to VGA addresses will be forwarded.
2
ISAEN
RW
ISA mode enable. This bit affects how the PCI1620 passes I/O cycles within the 64-Kbyte ISA range. This
bit is not common between sockets. When this bit is set, the PCI1620 does not forward the last 768 bytes
of each 1K I/O range to CardBus.
1
CSERREN
RW
CSERR enable. This bit controls the response of the PCI1620 to CSERR signals on the CardBus bus. This
bit is separate for each socket.
0 = CSERR is not forwarded to PCI SERR (default)
1 = CSERR is forwarded to PCI SERR.
This bit is global in nature and should be accessed only through function 0.
This is a PME context bit and can be cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then these bits are
cleared by the assertion of PRST or GRST.
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