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| 型號(hào)： | PCI4410A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC CARD AND OHCI CONTROLLER |
| 中文描述： | PC卡和OHCI控制器 |
| 文件頁(yè)數(shù)： | 190/198頁(yè) |
| 文件大?。?/td> | 892K |
| 代理商： | PCI4410A |
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9
–
38
Table 9
–
31. Isochronous Receive Context Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
31
bufferFill
RSC
When this bit is set to 1, received packets are placed back-to-back to completely fill each receive
buffer. When this bit is cleared, each received packet is placed in a single buffer. If bit 28
(multiChanMode) is set to 1, this bit must also be set to 1. The value of this bit must not be changed
while bit 10 (active) or bit 15 (run) is set to 1.
30
isochHeader
RSC
When this bit is set to 1, received isochronous packets include the complete 4-byte isochronous
packet header seen by the link layer. The end of the packet is marked with a xferStatus in the first
doublet, and a 16-bit timeStamp indicating the time of the most recently received (or sent) cycleStart
packet. When this bit is cleared, the packet header is stripped from received isochronous packets.
The packet header, if received, immediately precedes the packet payload. The value of this bit must
not be changed while bit 10 (active) or bit 15 (run) is set to 1.
29
cycleMatchEnable
RSCU
When this bit is set to 1, the context begins running only when the 13-bit cycleMatch field (bits 24
–
12)
in the isochronous receive context match register (see Section 9.43) matches the 13-bit cycleCount
field in the cycleStart packet. The effects of this bit, however, are impacted by the values of other bits
in this register. Once the context has become active, hardware clears this bit. The value of this bit
must not be changed while bit 10 (active) or bit 15 (run) is set to 1.
28
multiChanMode
RSC
When this bit is set to 1, the corresponding isochronous receive DMA context receives packets for all
isochronous channels enabled in the isochronous receive channel mask high (offset 70h/74h, see
Section 9.19) and isochronous receive channel mask low (offset 78h/7Ch, see Section 9.20)
registers. The isochronous channel number specified in the isochronous receive context match
register (see Section 9.43) is ignored.
When this bit is cleared, the isochronous receive DMA context receives packets for that single
channel. Only one isochronous receive DMA context can use the isochronous receive channel mask
registers (see Sections 9.19 and 9.20). If more that one isochronous receive context control register
has this bit set to 1, the results are undefined. The value of this bit must not be changed while bit 10
(active) or bit 15 (run) is set to 1.
27
–
16
RSVD
R
Reserved. Bits 27
–
16 return 0s when read.
15
run
RSCU
This bit is set by software to enable descriptor processing for the context and cleared by software to
stop descriptor processing. The PCI4410A device changes this bit only on a hardware or software
reset.
14
–
13
RSVD
R
Reserved. Bits 14 and 13 return 0s when read.
12
wake
RSU
Software sets this bit to cause the PCI4410A device to continue or resume descriptor processing.
The PCI4410A device clears this bit on every descriptor fetch.
11
dead
RU
The PCI4410A device sets this bit to 1 when it encounters a fatal error, and clears the bit when
software resets bit 15 (run).
10
active
RU
The PCI4410A device sets this bit to 1 when it is processing descriptors.
9
–
8
RSVD
R
Reserved. Bits 9 and 8 return 0 when read.
7
–
5
spd
RU
This field indicates the speed at which the packet was received.
000b = 100 Mbits/s
001b = 200 Mbits/s
010b = 400 Mbits/s
All other values are reserved.
4
–
0
event code
RU
For bufferFill mode, possible values are: ack_complete, evt_descriptor_read, evt_data_write, and
evt_unknown. Packets with data errors (either dataLength mismatches or dataCRC errors) and
packets for which a FIFO overrun occurred are backed out. For packet-per-buffer mode, possible
values are: ack_complete, ack_data_error, evt_long_packet, evt_overrun, evt_descriptor_read,
evt_data_write, and evt_unknown.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCI4510PDV | PC CARD AND INTEGRATED 1394A-2000 OHCI TWO PORT PHY/LINK LAYER CONTROLLER |
| PCI4515 | SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED |
| PCI4515GHK | SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED |
| PCI4515ZHK | SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED |
| PCI6420 | Integrated 2-Slot PC Card & Dedicated Flash Media Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI4410AGHK | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI INTEGRATED PC CARD RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI4410APDV | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI INTEGRATED PC CARD RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI4410GHK | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| PCI4410PDV | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PCI4450 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:PC Card and OHCI Controller |
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